HT67F60 datasheet(62/242 Pages) HOLTEK

62 / 242 page

Rev. 1.50

March 06 , 2012

Rev. 1.50

March 06 , 2012

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPRO

This is the high speed system oscillator ready flag which indicates when the high speed

system oscillator is stable. This flag is cleared to "0" by hardware when the device is

powered on and then changes to a high level after the high speed system oscillator is stable.

Therefore this flag will always be read as "1" by the application program after device

power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has

occurred, the flag will change to a high level after 1024 clock cycles if the HXT oscillator is

used and after 15~16 clock cycles if the ERC or HIRC oscillator is used.

Bit 1

IDLEN: IDLE Mode control

0: Disable

1: Enable

This is the IDLE Mode Control bit and determines what happens when the HALT

instruction is executed. If this bit is high, when a HALT instruction is executed the

device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but

the system clock will continue to keep the peripheral functions operational, if

FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop

in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT

instruction is executed.

Bit 0

HLCLK: system clock selection

0: fH/2 ~ fH/64 or fL

1: fH

This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fL clock is used as the

system clock. When the bit is high the fH clock will be selected and if low the fH/2 ~

fH/64 or fL clock will be selected. When system clock switches from the fH clock to the

fL clock and the fH clock will be automatically switched off to conserve power.

Fast Wake-up

To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system

clock source to the device will be stopped. However when the device is woken up again, it can take

a considerable time for the original system oscillator to restart, stabilise and allow normal operation

to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is

provided, which allows fSUB, namely either the LXT or LIRC oscillator, to act as a temporary clock

to first drive the system until the original system oscillator has stabilised. As the clock source for the

Fast Wake-up function is fSUB, the Fast Wake-up function is only available in the SLEEP1 and

IDLE0 modes. When the device is woken up from the SLEEP0 mode, the Fast Wake-up function

has no effect because the fSUB clock is stopped. The Fast Wake-up enable/disable function is

controlled using the FSTEN bit in the SMOD register.

If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up

function is enabled, then it will take one to two tSUB clock cycles of the LIRC or LXT oscillator for

the system to wake-up. The system will then initially run under the fSUB clock source until 1024

HXT clock cycles have elapsed, at which point the HTO flag will switch high and the system will

switch over to operating from the HXT oscillator.

If the ERC or EC or HIRC oscillators or LIRC oscillator is used as the system oscillator then it will

take 15~16 clock cycles of the ERC or EC or HIRC or 1~2 cycles of the LIRC to wake up the

system from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these

cases.

HT67F60 датащи(PDF) 62 Page - Holtek Semiconductor Inc

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