HT67F60 datasheet(69/242 Pages) HOLTEK

69 / 242 page

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM

Rev. 1.50

March 06 , 2012

Rev. 1.50

March 06 , 2012

Watchdog Timer

The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to

unknown locations, due to certain uncontrollable external events such as electrical noise.

Watchdog Timer Clock Source

The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by

one of two sources selected by configuration option: fSUB or fSYS/4. The fSUB clock can be sourced

from either the LXT or LIRC oscillators, again chosen via a configuration option. The Watchdog

Timer source clock is then subdivided by a ratio of 28 to 215 to give longer timeouts, the actual value

being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an

approximate period of 32kHz at a supply voltage of 5V.

However, it should be noted that this specified internal clock period can vary with VDD, temperature

and process variations. The LXT oscillator is supplied by an external 32.768kHz crystal. The other

Watchdog Timer clock source option is the fSYS/4 clock. The Watchdog Timer clock source can

originate from its own internal LIRC oscillator, the LXT oscillator or fSYS/4. It is divided by a value

of 28 to 215, using the WS2~WS0 bits in the WDTC register to obtain the required Watchdog Timer

time-out period.

Watchdog Timer Control Register

A single register, WDTC, controls the required timeout period as well as the enable/disable

operation. This register together with several configuration options control the overall operation of

the Watchdog Timer.

●

WDTC Register

Bit

Name

FSYSON

WS2

WS1

WS0

WDTEN3 WDTEN2 WDTEN1 WDTEN0

R/W

POR

Bit 7

FSYSON: fSYS Control in IDLE Mode

0: Disable

1: Enable

Bit 6 ~ 4

WS2, WS1, WS0: WDT time-out period selection

000: 256/fS

001: 512/fS

010: 1024/fS

011: 2048/fS

100: 4096/fS

101: 8192/fS

110: 16384/fS

111: 32768/fS

These three bits determine the division ratio of the Watchdog Timer source clock,

which in turn determines the timeout period.

Bit 3 ~ 0

WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT Software Control

1010: Disable

Other: Enable

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