TMS320LC2401AVFS datasheet(25/88 Pages) TI

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TMS320LF2401A, TMS320LC2401A

DSP CONTROLLERS

SPRS161K − MARCH 2001 − REVISED JULY 2007

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

interrupt request structure (continued)

Table 3. TMS320Lx2401A Interrupt Source Priority and Vectors (Continued)

INTERRUPT

NAME

OVERALL

PRIORITY

CPU

INTERRUPT

AND

VECTOR

ADDRESS

BIT

POSITION IN

PIRQRx AND

PIACKRx

PERIPHERAL

INTERRUPT

VECTOR

(PIV)

MASK-

ABLE?

SOURCE

PERIPHERAL

MODULE

DESCRIPTION

ADCINT

1.12

0004h

ADC

ADC interrupt

(low priority)

XINT1

INT6

000Ch

1.13

0001h

External

Interrupt Logic

External interrupt pins

XINT2

000Ch

1.14

0011h

External

Interrupt Logic

External interrupt pins

(low-priority mode)

Reserved

000Eh

N/A

CPU

Analysis interrupt

TRAP

N/A

0022h

N/A

CPU

TRAP instruction

Phantom

Interrupt

Vector

N/A

0000h

N/A

CPU

Phantom interrupt vector

INT8−INT16

N/A

0010h−0020h

N/A

CPU

Software interrupt vectors†

INT20−INT31

N/A

00028h−0603Fh

N/A

CPU

Software interrupt vectors†

† Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information.

NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details.

DSP CPU core

The TMS320Lx2401A device uses an advanced Harvard-type architecture that maximizes processing power

by maintaining two separate memory bus structures — program and data — for full-speed execution. This

multiple bus structure allows data and instructions to be read simultaneously. Instructions support data transfers

between program memory and data memory. This architecture permits coefficients that are stored in program

memory to be read in RAM. This, coupled with a four-deep pipeline, allows the Lx2401A device to execute most

instructions in a single cycle. See the functional block diagram of the 2401A DSP CPU for more information.

TMS320Lx2401A instruction set

The 2401A DSP implements a comprehensive instruction set that supports both numeric-intensive

signal-processing operations and general-purpose applications, such as multiprocessing and high-speed

control.

For maximum throughput, the next instruction is prefetched while the current one is being executed.

addressing modes

The TMS320Lx2401A instruction set provides four basic memory-addressing modes: direct, indirect,

immediate, and register.

In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field

is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address.

Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, with each

page containing 128 words.

Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address

of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers

(AR0 −AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary

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