TMS320LC2401AVFS datasheet(47/88 Pages) TI

47 / 88 page

TMS320LF2401A, TMS320LC2401A

DSP CONTROLLERS

SPRS161K − MARCH 2001 − REVISED JULY 2007

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

clock domains (continued)

Table 9. Low-Power Modes Summary

LOW-POWER MODE

LPMx BITS

SCSR1

[13:12]

CPU

CLOCK

DOMAIN

SYSTEM

CLOCK

DOMAIN

WDCLK

STATUS

PLL

STATUS

OSC

STATUS

FLASH

POWER

EXIT

CONDITION

CPU running normally

—

IDLE1 − (LPM0)

Off

Peripheral

Interrupt,

External Interrupt,

Reset,

PDPINTA

IDLE2 − (LPM1)

Off

Wakeup

Interrupts,

External Interrupt,

Reset,

PDPINTA

HALT − (LPM2)

[PLL/OSC power down]

Off

Off†

Reset,

PDPINTA

† The Flash must be powered down by the user code prior to entering LPM2. For more details, see the TMS320LF/LC240xA DSP Controllers

Reference Guide: System and Peripherals (literature number SPRU357).

other power-down options

2401A devices have clock-enable bits to the following on-chip peripherals: ADC, SCI, and EVA. Clock to these

peripherals are disabled after reset; thus, start-up power can be low for the device.

Depending on the application, these peripherals can be turned on/off to achieve low power.

Refer to the SCSR1 register for details on the peripheral clock enable bits.

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