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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320LC2401AVFS датащи(PDF) 75 Page - Texas Instruments |
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TMS320LC2401AVFS датащи(HTML) 75 Page - Texas Instruments |
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75 / 88 page  TMS320LF2401A, TMS320LC2401A DSP CONTROLLERS SPRS161K − MARCH 2001 − REVISED JULY 2007 75 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 10-bit analog-to-digital converter (ADC) The 10-bit ADC has a separate power bus for its analog circuitry. These pins are referred to as VCCA and VSSA. The power bus isolation is to enhance ADC performance by preventing digital switching noise of the logic circuitry that can be present on VSS and VCC from coupling into the ADC analog stage. All ADC specifications are given with respect to VSSA unless otherwise noted. Resolution 10-bit (1024 values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monotonic Assured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output conversion mode 000h to 3FFh (000h for VI ≤ VSSA; 3FFh for VI ≥ VCCA) . . . . . . . . . . . . . . . . . . . . . . . Conversion time (including sample time) 500 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions MIN NOM MAX UNIT VCCA† Analog supply voltage 3.0 3.3 3.6 V VSSA† Analog ground 0 V VAI Analog input voltage, ADCIN00−ADCIN04 VREFLO VREFHI V † VCCA and VSSA must be stable, within ±1/2 LSB of the required resolution, during the entire conversion time. ADC operating frequency MIN MAX UNIT ADC operating frequency 2 30 MHz operating characteristics over recommended operating condition ranges PARAMETER DESCRIPTION MIN TYP MAX UNIT IADCIN Analog input leakage 1 mA Cai Analog input capacitance Typical capacitive load on Non-sampling 10 pF Cai Analog input capacitance Typical capacitive load on analog input pin Sampling 30 pF EDNL Differential nonlinearity error Difference between the actual step width and the ideal value ±2 LSB EINL Integral nonlinearity error Maximum deviation from the best straight line through the ADC transfer characteristics, excluding the quantization error ±2 LSB td(PU) Delay time, power-up to ADC valid Time to stabilize analog stage after power-up 10 ms ZAI Analog input source impedance Analog input source impedance needed for conversions to remain within specifications at min tw(SH) 10 Ω Zero-offset error 8 10 LSB |
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