TMS320LC2401AVFS datasheet(64/88 Pages) TI

64 / 88 page

TMS320LF2401A, TMS320LC2401A

DSP CONTROLLERS

SPRS161K − MARCH 2001 − REVISED JULY 2007

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

external reference crystal/clock with PLL circuit enabled

timing with the PLL circuit enabled

PARAMETER

MIN

MAX

UNIT

Resonator

Input clock frequency†

Crystal

MHz

Input clock frequency†

CLKIN

MHz

† Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.

switching characteristics over recommended operating conditions [H = 0.5 tc(CO)] (see Figure 26)

PARAMETER

PLL MODE

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

X4 mode†

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

LF2401A

X4 mode† @ 2 mA load

H−3

H+3

tw(COH)

Pulse duration, CLKOUT high

LF2401A

X4 mode† @ 2 mA load

H−3

H+3

tw(COL)

Pulse duration, CLKOUT low

LC2401A

X4 mode† @ 2 mA load

H−5

H+5

tw(COH)

Pulse duration, CLKOUT high

LC2401A

X4 mode† @ 2 mA load

H−5

H+5

† Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 2 MHz minimum.

timing requirements (see Figure 26)

MIN

MAX

UNIT

tc(Cl)

Cycle time, XTAL1/CLKIN

250

tf(Cl)

Fall time, XTAL1/CLKIN

tr(Cl)

Rise time, XTAL1/CLKIN

tw(CIL)

Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl)

tw(CIH)

Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl)

XTAL1/CLKIN

tc(CI)

tw(CIL)

tw(CIH)

tf(Cl)

tr(Cl)

tc(CO)

tw(COH)

tw(COL)

tr(CO)

tf(CO)

CLKOUT

Figure 26. CLKIN-to-CLKOUT Timing With PLL and External Clock in

×4 Mode

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