TMS320LC2401AVFS datasheet(49/88 Pages) TI

49 / 88 page

TMS320LF2401A, TMS320LC2401A

DSP CONTROLLERS

SPRS161K − MARCH 2001 − REVISED JULY 2007

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

digital I/O control registers

Table 11 lists the registers available in the digital I/O module. As with other 2401A peripherals, these registers

are memory-mapped to the data space.

Table 11. Addresses of Digital I/O Control Registers

ADDRESS

NAME

7090h

MCRA

I/O MUX control register A

7098h

PADATDIR

I/O port A data and direction register

709Ah

PBDATDIR

I/O port B data and direction register

CAUTION:

The bit definitions of the MCRA, PADATDIR, and PBDATDIR registers are not compatible

with those of other 24x/240x/240xA devices.

watchdog (WD) timer module

The 2401A device includes a watchdog (WD) timer module. The WD function of this module monitors software

and hardware operation by generating a system reset if it is not periodically serviced by software by having the

correct key written. The WD timer operates independently of the CPU. It does not need any CPU initialization

to function. When a system reset occurs, the WD timer defaults to the fastest WD timer rate available (WDCLK

signal = CLKOUT/512). As soon as reset is released internally, the CPU starts executing code, and the WD timer

begins incrementing. This means that, to avoid a premature reset, WD setup should occur early in the power-up

sequence. See Figure 19 for a block diagram of the WD module. The WD module features include the following:

D WD Timer

−

Seven different WD overflow rates

−

A WD-reset key (WDKEY) register that clears the WD counter when a correct value is written, and

generates a system reset if an incorrect value is written to the register

−

WD check bits that initiate a system reset if an incorrect value is written to the WD control register

(WDCR)

D Automatic activation of the WD timer, once system reset is released

−

Three WD control registers located in control register frame beginning at address 7020h.

NOTE: All registers in this module are 8-bit registers. When a register is accessed, the register data is in the lower byte, the upper byte

is read as zeros. Writing to the upper byte has no effect.

Table 12 shows the different WD overflow (time-out) selections. Figure 19 shows the WD block diagram.

The watchdog can be disabled in software by writing ‘1’ to bit 6 of the WDCR register (WDCR.6) while bit 5 of

the SCSR2 register (SCSR2.5) is 1. If SCSR2.5 is 0, the watchdog will not be disabled. SCSR2.5 is equivalent

to the WDDIS pin of the TMS320F243/241 devices.

TMS320LC2401AVFS датащи(PDF) 49 Page - Texas Instruments

TMS320LC2401AVFS датащи(HTML) 49 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

датащи скачать

ссылки URL