MPC5602D Microcontroller Product Brief, Rev. 3.1

Preliminary—Subject to Change Without Notice

Device family overview

Freescale Semiconductor

20

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Up to 33 single ended inputs channels, expandable to 61 channels with external multiplexers

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Internally multiplexed channels

— up to 33 channels of which 16 high-accuracy

— Dedicated result register available for every internally muxed channel

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Externally multiplexed channels

— Internal control to support generation of external analog multiplexor selection

— 4 internal channels optionally used to support externally multiplexed inputs, providing

transparent control for additional ADC channels

— Each of the 4 channels supports up to 8 externally muxed inputs

— Individual dedicated result register also available for externally muxed conversion channels

— 3 independently configurable sample and conversion times for high occurrence channels,

internally muxed channels and externally muxed channels

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Support for one-shot, scan and injection conversion modes

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Independently configurable sampling duration for each type of channel

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Conversion triggering support

— Internal conversion triggering from periodic interrupt timer (PIT) or timed I/O module

(eMIOS) through cross triggering unit (CTU)

— Internal conversion triggering from periodic interrupt timer (PIT)

— 1 input pin configurable as external conversion trigger source

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Up to 6 configurable analog comparator channels offering range comparison with triggered alarm

— Greater than

—Less than

— Out of range

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All unused analog pins available as general purpose input pins

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Unused 12-bit ADC analog pins, with the exception of the 16 dedicated high accuracy channels,

available as general purpose output pins

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Power-down mode

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Supports DMA transfer of results based on end of conversion chain or each conversion

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Separate dedicated DMA request for injection mode

3.5.16

Enhanced Direct Memory Access Controller (eDMA)

The following summarizes the MPC5602D’s implementation of the eDMA controller:

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16 channels to support independent 8-, 16-, or 32-bit single value or block transfers

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Support of variable sized queues and circular queues

1. Please refer to the data sheet for up-to-date values on current consumption. This value is only estimates and has

not been validated.