MPC5602D Microcontroller Product Brief, Rev. 3.1

Preliminary—Subject to Change Without Notice

Device family overview

Freescale Semiconductor

12

•

1 enhanced full CAN (FlexCAN) module with configurable buffers

•

Up to 79 configurable general purpose pins supporting input and output operations (package

dependent)

•

Real-Time Counter (RTC)

— Clock source from internal 128 kHz or 16 MHz oscillator supporting autonomous wakeup with

1 ms resolution with maximum timeout of 2 seconds

•

Up to 4 periodic interrupt timers (PIT) with 32-bit counter resolution

•

Device/board boundary scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE

1149.1)

•

On-chip voltage regulator (VREG) for regulation of input supply for all internal levels

3.5

Module features

The following sections provide more details of the modules implemented on the MPC5602D.

3.5.1

e200z0h core processor

The e200z0h core includes the following features:

•

High performance, low cost e200z0h core processor for managing peripherals and interrupts

•

Single issue 4-stage pipelined in-order execution, 32-bit Power Architecture CPU

•

Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions

— Results in efficient code size footprint

— Minimizes impact on performance

•

Branch processing acceleration using lookahead instruction buffer

•

Load/store unit

— 1-cycle load latency

— Misaligned access support

— No load-to-use pipeline bubbles

•

Thirty-two 32-bit general purpose registers (GPRs)

•

Separate instruction bus and load/store bus Harvard architecture with separate instruction and

load/store buses

•

Hardware vectored interrupt support

•

Reservation instructions for implementing read-modify-write constructs

•

Multi-cycle divide word (divw), and load multiple word (lmw) store multiple word (smw) multiple

class instructions, can be interrupted to prevent increases in interrupt latency

•

Nexus1 support