MPC5674F datasheet(44/132 Pages) FREESCALE

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MPC5674F Microcontroller Data Sheet, Rev. 6

Electrical Characteristics

Freescale Semiconductor

Table 28. MPC5674F Operating Frequencies1, 2

1 The values in the table are specified at:

VDD = 1.02 V to 1.32 V

VDDE = 3.0 V to 3.6 V

VDDEH = 4.5 V to 5.5 V

VDD33 and VDDSYN = 3.0 V to 3.6 V

TA =TL to TH.

2 Up to the maximum frequency rating of the device (refer to Table 1). The f

sys speed is the nominal maximum frequency.

270 Mhz parts allow for 264 Mhz system clock + 2% FM.

Mode

SIU_ECCR

[EBDF[0:1]]3

3 See the MPC5674F Reference Manual for full description as not all bit combinations are valid.

fsys

(core)

fplatf

(platform and all blocks

except eTPU)

fetpu

(eTPU, eTPU RAM,

and NDEDI)

febi_cal

4,5

4 EBI/Calibration bus is not available in all packages.

5 The EBI/Calibration Bus operating frequency, f

ebi_cal , depends on clock divider settings of block’s max allowed

frequency of operation. Normally febi_cal =fplatf /2, but can be limited to < fplatf /2 in Full Mode.

Unit

Enhanced

264

132

MHz

Full

200

100

200

MHz

Legacy

132

MHz

Table 29. IPCLKDIV Settings

SIU_SYSDIV

[IPCLKDIV[0:1]]

Mode

Description

Enhanced

CPU frequency is doubled (Max 264Mhz). Platform,

peripheral, and eTPU clocks are 1/2 of CPU frequency

Full

CPU and eTPU frequency is doubled (Max 200Mhz).

Platform and peripheral clocks are 1/2 of CPU frequency.

—

Reserved

Legacy

CPU, eTPU, platform, and peripheral’s clocks all run at

same speed (Max 132Mhz).

Table 30. SYSCLKDIV Settings

SIU_SYSDIV

[SYSCLKDIV[0:1]]

Description

Divide by 2.

Divide by 4.

Divide by 8.

Divide by 16.

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