MPC5674F datasheet(37/132 Pages) FREESCALE

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Electrical Characteristics

MPC5674F Microcontroller Data Sheet, Rev. 6

Freescale Semiconductor

Frequency un-LOCK Range

fUL

–4.0

4.0

% fsys

Frequency LOCK Range

fLCK

–2.0

2.0

% fsys

D_CLKOUT Period Jitter10, 11 Measured at fSYS Max

Cycle-to-cycle Jitter

CJitter

–5

%fclko

Peak-to-Peak Frequency Modulation Range Limit 12,13

(fsys Max must not be exceeded)

Cmod

%fsys

FM Depth Tolerance14

Cmod_err

–0.25

0.25

%fsys

VCO Frequency

fVCO

192

600

MHz

Modulation Rate Limits15

fmod

0.400

MHz

Predivider output frequency range16

fprediv

410

MHz

1 All values given are initial design targets and subject to change.

2 Crystal and External reference frequency limits depend on device relying on PLL to lock prior to release of reset, default

PREDIV/EPREDIV, MFD/EMFD default settings, and VCO frequency range. Absolute minimum loop frequency is 4 MHz.

3 Upper tolerance of less than 1% is allowed on 40MHz crystal.

4 All internal registers retain data at 0 Hz.

5 “Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.

6 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f

LOR. This

frequency is measured at D_CLKOUT with the divider set to divide-by-2 of the system clock. NOTE: in SCM, the PLL is running

open loop at a centercode 0x4. The MFD has no effect and the RFD is bypassed.

7 This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the

synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal

startup time.

For Flexray operation, duty cycle requirements are higher.

9 Duty cycle can be 20–80% when PLL is used with a pre-divider greater than 1.

10 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

sys.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the Cjitter

percentage for a given interval. D_CLKOUT divider set to divide-by-2.

11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C

jitter +Cmod.

12 Modulation depth selected must not result in f

pll value greater than the fpll maximum specified value.

13 Maximum and minimum variation from programmed modulation depth is pending characterization. Depth settings available in

control register are: 1%, 2%, 3%, and 4% peak-to-peak.

14 Depth tolerance is the programmed modulation depth ±0.25% of F

sys. Initial design target pending silicon evaluation.

15 Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz

will result in reduced calibration accuracy.

16 Violating this range will cause the VCO max/min range to be violated with the default MFD settings out of reset.

Table 18. FMPLL Electrical Specifications1 (continued)

(VDDSYN = 3.0 V to 3.6 V, VSS =VSSSYN =0 V, TA =TL to TH)

Spec

Characteristic

Symbol

Min

Max

Unit

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