Data Sheet

7

Rev. 1.2, 2007-11-13

TLE7269G

Functional Description

4

Functional Description

The LIN Bus is a single wire, bi-directional bus, used for in-vehicle networks. The LIN Transceiver TLE7269G is

the interface between the microcontroller and the physical LIN Bus (see Figure 17 and Figure 18). The logical

values of the microcontroller are driven to the LIN bus via the TxD inputs of the TLE7269G. The transmit data

stream on the TxD input is converted to a LIN bus signal with optimized slew rate to minimize the EME level of the

LIN network. The RxD outputs read back the information from the LIN bus to the microcontroller. The receiver has

an integrated filter network to suppress noise on the LIN Bus and to increase the EMI (Electro Magnetic Immunity)

level of the transceiver.

Two logical states are possible on the LIN bus according to the LIN Specification 2.1 (see Figure 3):

In dominant state, the voltage on the LIN bus is set to the GND level. In recessive state, the voltage on the LIN

bus is set to the supply voltage

V

generates a dominant level on the BUS1, BUS2 LIN interface pins. The RxD1, RxD2 outputs read back the signal

on the LIN bus and indicate a dominant signal on the LIN bus with a logical “Low” to the microcontroller. Setting

the TXD1, TxD2 pins to “High” the transceiver TLE7269G sets the BUS1, BUS2 LIN interface pins to recessive

level, at the same time the recessive level on the LIN bus is indicated by a logical “High” on the RxD1, RxD2

outputs.

Every LIN network consists of a master node and one or more slave nodes. To configure the TLE7269G for master

node applications, a resistor in the range of 1 k

Ω and a reverse diode must be connected between the LIN bus

and the power supply

V

Both integrated transceivers can operate independent from each other and several operation modes and Wake-

Up functions are implemented. The bus Wake-Up function of the transceiver 2 can be turned off via the W2O pin.

Figure 3

LIN bus signals

t

TxD1

TxD2

V

IO

Recessive

Recessive

BUS1

BUS2

V

S

Recessive

Dominant

Recessive

t

t

V

IO

Recessive

Recessive

RxD1

RxD2

Dominant

Dominant