TLE6240GP

Smart 16-Channel Low-Side Switch

Electrical and Functional Description of Blocks

Data Sheet

20

Rev.3.3, 2010-02-15

diagnostic information out of the shift register on the rising edge of serial clock. It is essential that the SCLK pin is

in a logic low state whenever chip select CS makes any transition.

SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI information is read in on

the falling edge of SCLK. Input data is latched in the shift register and then transferred to the control buffer of the

output stages.

The input data consist of 16 bit, made up of one control byte and one data byte. The control byte is used to program

the device, to operate it in a certain mode as well as providing diagnostic information (see Chapter 6.2). The eight

data bits contain the input information for the eight channels, and are high active.

SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit first. SO is in a

high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO pin

following the rising edge of SCLK.