TLE6240GP

Smart 16-Channel Low-Side Switch

Electrical and Functional Description of Blocks

Data Sheet

18

Rev.3.3, 2010-02-15

5.5

SPI Interface

Electrical Characteristics: SPI Interface

V

all voltages with respect to ground, positive current flowing into pin

Pos.

Parameter

Symbol

Limit Values

Unit

Conditions

Min.

Typ.

Max.

5.5.1

Input Pull-down Current (SI, SCLK)

I

20

50

µA–

5.5.2

Input Pull-up Current (CS)

I

IN(CS)

10

20

50

µA–

5.5.3

SO High State Output Voltage

V

SOH

V

–

V

I

5.5.4

SO Low State Output Voltage

V

SOL

––

0.4

V

I

5.5.5

Output Tri-state Leakage Current

I

SOlkg

-10

0

10

µACS = H;

0

5.5.6

Serial Clock Frequency

(depending on SO load)

f

SCK

DC

–

5

MHz

–

5.5.7

Serial Clock Period (1/

f

t

p(SCK)

200

–

–

ns

–

5.5.8

Serial Clock High Time

t

SCKH

50

–

–

ns

–

5.5.9

Serial Clock Low Time

t

SCKL

50

–

–

ns

–

5.5.10

Enable Lead Time (falling edge of

CS to rising edge of CLK)

t

lead

200

–

–

ns

–

5.5.11

Enable Lag Time (falling edge of

CLK to rising edge of CS)

t

lag

200

–

–

ns

–

5.5.12

Data Setup Time (required time SI

to falling of CLK)

t

SU

20

–

–

ns

–

5.5.13

Data Hold Time (falling edge of

CLK to SI)

t

H

20

–

–

ns

–

5.5.14

Disable Time (@

C

1)

1) This parameter will not be tested but specified by design

t

DIS

––

150

ns

–

5.5.15

(CS high time between two

accesses)

2) This time is necessary between two write accesses to control e.g. channel 1 to 8 during the first access and channel 9 to

16 during the second access. To get the correct diagnostic information, the transfer delay time has to be extended to the

maximum fault delay time

t

t

dt

200

–

–

ns

–

5.5.16

Data Valid Time

t

valid

––

100

ns

C

1)

––

120

ns

C

1)

––

150

ns

C

1)