Data Sheet

19

Rev.3.3, 2010-02-15

TLE6240GP

Smart 16-Channel Low-Side Switch

Electrical and Functional Description of Blocks

Figure 12

Input Timing Diagram

Figure 13

SO Valid Time Waveforms and Enable and Disable Time Waveforms

SPI Signal Description

CS - Chip Select. The system microcontroller selects the TLE6240GP by means of the CS pin. Whenever the pin

is in a logic low state, data can be transferred from the

µC and vice versa.

•

CS High to Low Transition:

– diagnostic status information is transferred from the power outputs into the shift register

– serial input data can be clocked in from then on

– SO changes from high impedance state to logic high or low state corresponding to the SO bits

•

CS Low to High Transition:

– transfer of SI bits from shift register into output buffers

To avoid any false clocking the serial clock input pin SCLK should be logic low state during high to low transition

of CS. When CS is in a logic high state, any signals at the SCLK and SI pins are ignored and SO is forced into a

high impedance state.

SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE6240GP. The serial input

(SI) accepts data into the input shift register on the falling edge of SCLK while the serial output (SO) shifts

CS

SCLK

SI

0.7VS

0.7VS

SCLK

CS

SO

SO

SO