S5000PAL datasheet(26/112 Pages) INTEL

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Intel

® Server Board S5000PAL / S5000XAL TPS

Functional Architecture

Revision 1.7

Intel order number: D31979-010

a total read bandwidth of 21GB/s for four FB-DIMM channels. Thus, this provides 10.7 GB/s of write

memory bandwidth for four FB-DIMM channels. The total bandwidth is based on read bandwidth thus the

total bandwidth is 17 GB/s for 533 and 21.0 GB/s for 667.

On the Intel® Server Board S5000PAL / S5000XAL, a pair of channels becomes a branch where Branch

0 consists of channels A and B, and Branch 1 consists of channels C and D. FBD memory channels are

organized into two branches for support of RAID 1(mirroring).

TP02299

DIMM

Branch 0

MCH

Channel A

Channel B

Channel D

Channel C

Branch 1

Figure 11. Memory Layout

To boot the system, the system BIOS on the server board uses a dedicated I

2C bus to retrieve DIMM

information needed to program the MCH memory registers. The following table provides the I

addresses for each DIMM slot.

Table 1. I

2C Addresses for Memory Module SMB

Device

Address

DIMM A1

0xA0

DIMM A2

0xA2

DIMM B1

0xA0

DIMM B2

0xA2

DIMM C1

0xA0

DIMM C2

0xA2

DIMM D1

0xA0

DIMM D2

0xA2

3.1.3.1

Memory RASUM Features

The MCH supports several memory RASUM (Reliability, Availability, Serviceability, Usability, and

Manageability) features. These features include the Intel

® x4 Single Device Data Correction (Intel® x4

SDDC) for memory error detection and correction, Memory Scrubbing, Retry on Correctable Errors,

Memory Built In Self Test, DIMM Sparing, and Memory Mirroring. See the Intel

® S5000 Series Chipsets

Server Board Family Datasheet

for more information describing these features.

3.1.3.2

Supported Memory

The server board supports up to eight DDR2-533 or DDR2-667 Fully Buffered DIMMs (FBD memory).

The following tables show the maximum memory configurations supported using the specified memory

technology.

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