IXP46X datasheet(60/148 Pages) INTEL

60 / 148 page

Package Information

August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

ETHB_TXDATA[3:0] /

SMII_TXDATA[0] /

SMII_TXDATA[1] /

SMII_TXDATA[2] /

SMII_TXDATA[3]

MII Mode of Operation:

Transmit data bus to PHY, asserted synchronously with respect to ETHB_TXCLK. This MAC

interface does not contain hardware hashing capabilities local to the interface.

SMII Mode of Operation:

Each SMII_TXDATA line is an interface to a separate physical port.

ETHB_TXDATA[3] is multiplexed with SMII_TXDATA[3],

ETHB_TXDATA[2] is multiplexed with SMII_TXDATA[2],

ETHB_TXDATA[1] is multiplexed with SMII_TXDATA[1],

ETHB_TXDATA[0] is multiplexed with SMII_TXDATA[0]

The data on these signal are transmitted synchronously with respect to the rising edge of

SMII_CLK when operating as an SMII interface and synchronously with respect to the rising edge

of SMII_TXCLK when operating as a Source Synchronous SMII interface

ETHB_TXEN /

SMII_TXCLK

MII Mode of Operation:

Indicates that the PHY is being presented with nibbles on the MII interface. Asserted

synchronously, with respect to ETHB_TXCLK, at the first nibble of the preamble and remains

asserted until all the nibbles of a frame are presented. This MAC interface does not contain

hardware hashing capabilities local to the interface.

SMII Mode of Operation:

125-MHz clock that is used to send data to a physical interface when operating in a Source

Synchronous SMII mode of operation.

ETHB_RXCLK /

SMII_RXCLK

ZVI

MII Mode of Operation:

Externally supplied receive clock.

• 25 MHz for 100 Mbps operation

• 2.5 MHz for 10 Mbps operation

This MAC interface does not contain hardware hashing capabilities local to the interface.

SMII Mode of Operation:

125-MHz clock that is used to sample data being received from a physical interface when

operating in a Source Synchronous SMII mode of operation.

When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor.

Table 15.

MII/SMII Interfaces (Sheet 2 of 7)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

††

Please refer to Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired

IXP46X датащи(PDF) 60 Page - Intel Corporation

IXP46X датащи(HTML) 60 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL