IXP46X datasheet(59/148 Pages) INTEL

59 / 148 page

Package Information

August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

UTP_IP_ADDR[4:0]

I/O

Receive PHY address bus.

Used by the processor when operating in MPHY mode to poll and select a single PHY at any one

given time.

UTP_IP_FCO

TRI

UTOPIA Input Data Flow Control Output signal: Also known as the RX_ENB_N.

In SPHY configurations, UTP_IP_FCO is used to inform the PHY that the processor is ready to

accept data.

In MPHY configurations, UTP_IP_FCO is used to select which PHY will drive the UTP_RX_DATA and

UTP_RX_SOC signals. The PHY is selected by placing the PHY’s address on the UTP_IP_ADDR and

bringing UTP_OP_FCO to logic 1 during the current clock, followed by the UTP_OP_FCO going to a

logic 0 on the next clock cycle.

When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor.

Table 15.

MII/SMII Interfaces (Sheet 1 of 7)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

ETHB_TXCLK /

SMII_CLK

ZVI

MII Mode of Operation:

Externally supplied transmit clock.

• 25 MHz for 100 Mbps operation

• 2.5 MHz for 10 Mbps operation

This MAC interface does not contain hardware hashing capabilities local to the interface.

SMII Mode of Operation:

125-MHz input clock used as the reference clock when operating in SMII or Source Synchronous

SMII mode of operation.

When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor.

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

††

Please refer to Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual for information on how to select the interface desired

Table 14.

UTOPIA Level 2/MII_A/ SMII Interface (Sheet 7 of 7)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

††

For information on selecting the desired interface, see the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual.

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