IXP46X datasheet(54/148 Pages) INTEL

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August 2006

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet

Document Number: 306261-004US

UTP_OP_DATA[4] /

ETHA_TXEN

TRI

UTOPIA Mode of Operation:

UTOPIA output data. Also known as UTP_TX_DATA. Used to send data from the processor to an

ATM UTOPIA Level 2-compliant PHY.

MII Mode of Operation:

Indicates that the PHY is being presented with nibbles on the MII interface. Asserted

synchronously, with respect to ETHA_TXCLK, at the first nibble of the preamble, and remains

asserted until all the nibbles of a frame are presented. This MAC does not contains hardware

hashing capabilities local to the interface.

SMII mode of operation:

Not used.

UTP_OP_DATA[6:5]

TRI

UTOPIA Mode of Operation:

UTOPIA output data. Also known as UTP_TX_DATA. Used to send data from the processor to an

ATM UTOPIA Level 2-compliant PHY.

UTP_OP_DATA[7] /

SMII_TXDATA[4]

TRI

UTOPIA Mode of Operation:

UTOPIA output data. Also known as UTP_TX_DATA. Used to send data from the processor to an

ATM UTOPIA Level 2-compliant PHY.

MII Mode of Operation:

Not used.

SMII mode of operation:

Output data for SMII interface number four. The data on this signal is transmitted synchronously

with respect to the rising edge of SMII_CLK when operating as an SMII interface and

synchronously with respect to the rising edge of SMII_TXCLK when operating as a Source

Synchronous SMII interface

UTP_OP_ADDR[4:0]

I/O

Transmit PHY address bus. Used by the processor when operating in MPHY mode to poll and select

a single PHY at any given time.

When this interface/signal is enabled and is not being used in a system design, the interface/

signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the UTOPIA

and/or the NPE-A Ethernet soft fuse (refer to Expansion Bus Controller chapter of the Intel®

IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual) and is not

being used in a system design, this interface/signal is not required for any connection.

Table 14.

UTOPIA Level 2/MII_A/ SMII Interface (Sheet 2 of 7)

Name

Power

Reset†

Normal

After

Reset

Until

Software

Enables

Possible

Configur

ations

After

Software

Enables

Type†

Description

Note:

This table discusses all features supported on the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors. For details on feature support listed by processor,

see Table 1 on page 13.

†

For a legend of the Type codes, see Table 8 on page 43.

††

For information on selecting the desired interface, see the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual.

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