IXP46X datasheet(18/148 Pages) INTEL

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Datasheet

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Datasheet

August 2006

Document Number: 306261-004US

3.1

Key Functional Units

The following sections briefly describe the functional units and their interaction in the

system. For more detailed information, refer to the Intel® IXP45X and Intel® IXP46X

Product Line of Network Processors Developer’s Manual.

Unless otherwise specified, the functional descriptions apply to all of the IXP45X/

IXP46X network processors. For specific information on supported interfaces, refer to

Table 1 on page 13. For model-specific block diagrams, see Figure 1 on page 15,

Figure 2 on page 16, and Figure 3 on page 17.

3.1.1

Network Processor Engines (NPEs)

The network processor engines (NPEs) are dedicated-function processors containing

hardware coprocessors integrated into the IXP45X/IXP46X network processors. The

NPEs are used to off load processing function required by the Intel XScale® processor.

These NPEs are high-performance, hardware-multi-threaded processors with additional

local-hardware-assist functionality used to off load highly processor-intensive functions

such as MII (MAC), CRC checking/generation, AAL segmentation and re-assembly, AES,

AES-CCM, DES, 3DES, SHA, MD-5, etc.

All instruction code for the NPEs are stored locally and is accessed using a dedicated

instruction memory bus. Likewise, a separate dedicated data memory bus allows

accesses to local code store as well as DDR SDRAM via the AHB bus.

These NPEs support processing of the dedicated peripherals that can include:

• One UTOPIA Level 2 (Universal Test and Operation PHY Interface for ATM) interface

• Two High-Speed Serial (HSS) interfaces

• Up to three Media-Independent Interface (MII), up to three Serial Media

Independent Interfaces (SMII), or some combination of each.

Table 3 specifies the possible combination of interfaces for the NPEs contained on the

IXP45X/IXP46X network processors. These configurations are determined by the

factory programmed fuse settings or by software that configures the part during boot-

up (see the Expansion Bus Configuration Register 1 (EXP_CNFG1) in the Expansion Bus

Chapter of the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Developer’s Manual for more details). The table assumes that all features are

supported on the processor. For details on feature support listed by processor, see

Table 1 on page 13.

Table 3.

Network Processor Functions

Device

UTOPIA

HSS

MII /

SMII A

MII /

SMII B

MII /

SMII C

AES /

DES /

3DES

HDLC

SHA, MD-

Configuration 0

MII

Configuration 1

SMII

MII

Configuration 2

SMII

Configuration 3

MII

Configuration 4

MII

SMII

MII

Configuration 5

MII

SMII

Configuration 6

SMII

Configuration 7

SMII

MII

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