IXP46X datasheet(27/148 Pages) INTEL

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

August 2006

Datasheet

Document Number: 306261-004US

Datasheet—Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

The interfaces can be configured to support speeds from 1,200 Baud to 921 Kbaud. The

interfaces support configurations of:

• Five, six, seven, or eight data-bit transfers

• One or two stop bits

• Even, odd, or no parity

The request-to-send (RTS_N) and clear-to-send (CTS_N) modem control signals also

are available with the interface for hardware flow control.

3.1.12

GPIO

16 GPIO pins are supported by the IXP45X/IXP46X network processors. GPIO pins 0

through 15 can be configured to be general-purpose input or general-purpose output.

Additionally, GPIO pins 0 through 12 can be configured to be an interrupt input.

GPIO Pin 1 can also be configured as a clock input for an external USB 2.0 Host Bypass

clock. When spread spectrum clocking (SSC) is used, an external clock should be used

as the source for the USB 2.0 Host clock. Refer to the Intel® IXP45X and Intel® IXP46X

Product Line of Network Processors Developer’s Manual for more information.

GPIO Pin 14 and GPIO 15 can also be configured as a clock output. The output-clock

configuration can be set at various speeds, up to 33.33 MHz, with various duty cycles.

GPIO Pin 14 is configured as an input, upon reset. GPIO Pin 15 is configured as an

output, upon reset. GPIO Pin 15 can be used to clock the expansion interface, after

reset.

Several other GPIO pins can serve as an alternate function, as outlined in Table 5.

Table 5.

GPIO Alternate Function Table

GPIO Pin Number

GPIO function

Alternate Function

0†