IXP45X datasheet(117/148 Pages) INTEL

117 / 148 page

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

August 2006

Datasheet

Document Number: 306261-004US

117

Datasheet—Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

Figure 18.

PCI Input Timing

Table 53.

PCI Bus Signal Timings

Symbol

Parameter

33 MHz

66 MHz

Units

Notes

Min.

Max.

Min.

Max.

Tclk2outb

Clock to output for all bused

signals. This is the PCI_AD[31:0],

PCI_CBE_N [3:0], PCI_PAR,

PCI_FRAME_N, PCI_IRDY_N,

PCI_TRDY_N, PCI_STOP_N,

PCI_DEVSEL_N, PCI_PERR_N,

PCI_SERR_N

211

1, 2, 5,

7, 8

Tclk2out

Clock to output for all point-to-

point signals. This is the

PCI_GNT_N and PCI_REQ_N(0)

only.

212

1, 2, 5,

7, 8

Tsetupb

Input setup time for all bused

signals. This is the PCI_AD[31:0],

PCI_CBE_N [3:0], PCI_PAR,

PCI_FRAME_N, PCI_IRDY_N,

PCI_TRDY_N, PCI_STOP_N,

PCI_DEVSEL_N, PCI_PERR_N,

PCI_SERR_N

4, 6, 7,

Tsetup

Input setup time for all point-to-

point signals. This is the

PCI_REQ_N and PCI_GNT_N(0)

only.

10, 12

3, 4, 7,

Thold

Input hold time from clock.

4, 7, 8

Trst-off

Reset active-to-output float delay

5, 6, 7,

Notes:

See the timing measurement conditions.

Parts compliant to the 3.3 V signaling environment.

REQ# and GNT# are point-to-point signals and have different output valid delay and input setup

times than do bused signals. GNT# has a setup of 10 ns for 33 MHz and 5 ns for 66 MHz; REQ# has

a setup of 12 ns for 33 MHz and 5 ns for 66 MHz.

RST# is asserted and de-asserted asynchronously with respect to CLK.

All PCI outputs must be asynchronously driven to a tri-state value when RST# is active.

Setup time applies only when the device is not driving the pin. Devices cannot drive and receive

signals at the same time.

Timing was tested with a 70-pF capacitor to ground.

For additional information, see the PCI Local Bus Specification, Revision 2.2.

A9573-01

CLK

Input

Inputs

Valid

Thold

Tsetup(b)

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