SST25VF080B datasheet(8/32 Pages) SST

8 / 32 page

Data Sheet

8 Mbit SPI Serial Flash

SST25VF080B

S71296-04-000

01/10

Instructions

Instructions are used to read, write (Erase and Program),

and configure the SST25VF080B. The instruction bus

cycles are 8 bits each for commands (Op Code), data, and

addresses. Prior to executing any Byte-Program, Auto

Address Increment (AAI) programming, Sector-Erase,

Block-Erase, Write-Status-Register, or Chip-Erase instruc-

tions, the Write-Enable (WREN) instruction must be exe-

cuted first. The complete list of instructions is provided in

Table 5. All instructions are synchronized off a high to low

transition of CE#. Inputs will be accepted on the rising edge

of SCK starting with the most significant bit. CE# must be

driven low before an instruction is entered and must be

driven high after the last bit of the instruction has been

shifted in (except for Read, Read-ID, and Read-Status-

before receiving the last bit of an instruction bus cycle, will

terminate the instruction in progress and return the device

to standby mode. Instruction commands (Op Code),

addresses, and data are all input from the most significant

bit (MSB) first.

TABLE

5: Device Operation Instructions

Instruction

Description

Op Code Cycle1

1. One bus cycle is eight clock periods.

Address

Cycle(s)2

2. Address bits above the most significant bit of each density can be VIL or VIH.

Dummy

Cycle(s)

Data

Cycle(s)

Read

Read Memory

0000 0011b (03H)

1 to

∞

High-Speed Read

Read Memory at higher speed

0000 1011b (0BH)

1 to

∞

4 KByte Sector-Erase3

3. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.

Erase 4 KByte of

memory array

0010 0000b (20H)

32 KByte Block-Erase4

4. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.

Erase 32 KByte block

of memory array

0101 0010b (52H)

64 KByte Block-Erase5

5. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.

Erase 64 KByte block

of memory array

1101 1000b (D8H)

Chip-Erase

Erase Full Memory Array

0110 0000b (60H) or

1100 0111b (C7H)

Byte-Program

To Program One Data Byte

0000 0010b (02H)

AAI-Word-Program6

6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be

programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be programmed into the

initial address [A23-A1] with A0=1.

Auto Address Increment

Programming

1010 1101b (ADH)

2 to

∞

RDSR7

7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.

Read-Status-Register

0000 0101b (05H)

1 to

∞

EWSR

Enable-Write-Status-Register

0101b 0000b (50H)

WRSR

Write-Status-Register

0000 0001b (01H)

WREN

Write-Enable

0000 0110b (06H)

WRDI

Write-Disable

0000 0100b (04H)

RDID8

8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID and

device ID output stream is continuous until terminated by a low-to-high transition on CE#.

Read-ID

1001 0000b (90H) or

1010 1011b (ABH)

1 to

∞

JEDEC-ID

JEDEC ID read

1001 1111b (9FH)

3 to

∞

EBSY

Enable SO to output RY/BY#

status during AAI programming

0111 0000b (70H)

DBSY

Disable SO to output RY/BY#

status during AAI programming

1000 0000b (80H)

T5.0

1296

SST25VF080B датащи(PDF) 8 Page - Silicon Storage Technology, Inc

SST25VF080B датащи(HTML) 8 Page - Silicon Storage Technology, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

датащи скачать

ссылки URL