SST25VF080B datasheet(17/32 Pages) SST

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Data Sheet

8 Mbit SPI Serial Flash

SST25VF080B

S71296-04-000

01/10

Write-Enable (WREN)

The Write-Enable (WREN) instruction sets the Write-

Enable-Latch bit in the Status Register to 1 allowing Write

operations to occur. The WREN instruction must be exe-

cuted prior to any Write (Program/Erase) operation. The

WREN instruction may also be used to allow execution of

the Write-Status-Register (WRSR) instruction; however,

the Write-Enable-Latch bit in the Status Register will be

cleared upon the rising edge CE# of the WRSR instruction.

CE# must be driven high before the WREN instruction is

executed.

FIGURE 17: Write Enable (WREN) Sequence

Write-Disable (WRDI)

The Write-Disable (WRDI) instruction resets the Write-

Enable-Latch bit and AAI bit to 0 disabling any new Write

operations from occurring. The WRDI instruction will not

terminate any programming operation in progress. Any pro-

gram operation in progress may continue up to TBP after

executing the WRDI instruction. CE# must be driven high

before the WRDI instruction is executed.

FIGURE 18: Write Disable (WRDI) Sequence

Enable-Write-Status-Register (EWSR)

The Enable-Write-Status-Register (EWSR) instruction

arms the Write-Status-Register (WRSR) instruction and

opens the status register for alteration. The Write-Status-

execution of the Enable-Write-Status-Register instruction.

This two-step instruction sequence of the EWSR instruc-

tion followed by the WRSR instruction works like SDP (soft-

ware data protection) command structure which prevents

any accidental alteration of the status register values. CE#

must be driven low before the EWSR instruction is entered

and must be driven high before the EWSR instruction is

executed.

CE#

SCK

01 2 3 4 5 6 7

HIGH IMPEDANCE

MODE 0

MODE 3

1296 WREN.0

MSB

CE#

SCK

01 2 3 4 5 6 7

HIGH IMPEDANCE

MODE 0

MODE 3

1296 WRDI.0

MSB

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