TLK6002 datasheet(24/96 Pages) TI

24 / 96 page

DataIn

DataOut

SyncReset

TXAP

TXAN

RXAP

RXAN

TRANSMITTER

RECEIVER

MEDIA

50 W

GND

0.8* VDDT

TransmissionLine

50 W

TLK6002

SLLSE34 – MAY 2010

www.ti.com

Figure 2-6. 7-Degree Polynomial Scrambler

2.10 Power Down Mode

The TLK6002 can be put in power down either through device input pins or through MDIO control register

(1.15). PD_TRXA_N: Active low, powers down channel A. PD_TRXB_N: Active low, powers down channel

The MDIO management serial interface remains operational when in register based power down mode

(1.15 asserted for both channels), but status bits may not be valid since the clocks are disabled. The serial

outputs and parallel output interface signals are high impedance when in power down mode. See the

detailed per pin description for behavior of each device I/O signal during pin based and register based

power down.

2.11 Parallel to Serial (Transmit):

In the transmit direction, the device accepts parallel input data on the TDA_[19:0] and TDB_[19:0] input

pins and converts the data into an optionally scrambled 8b/10b encoded serial stream on the TXAP/N and

TXBP/N serial output pins.

2.12 Serial to Parallel (Receive)

Serial data is received on the RXAP/N and RXBP/N pins, and optionally descrambled and 8b/10b

decoded and converted to parallel output data pins RDA_[19:0] and RDB_[19:0]. The interpolator and

clock recovery circuit will lock to the data stream if the incoming serial rate is within ±200 PPM of the

reference clock for the channel. The recovered byte clock is used to retime and deserialize the input data

stream, and is always synchronous with the parallel output data.

2.13 High Speed CML Output

The high speed data output driver is implemented using Current Mode Logic (CML) with integrated pull up

resistors, requiring no external components. The transmit outputs must be AC coupled.

Figure 2-7. Example of High Speed I/O AC Coupled Mode (Channel A is shown).

Description

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