TLK6002 datasheet(84/96 Pages) TI

84 / 96 page

TLK6002

SLLSE34 – MAY 2010

www.ti.com

–

Write 1’b1 to 4.3 DATAPATH_RESET

•

Enable Test Pattern Verification:

–

Write 1’b1 to 7.12 TP_VERIFY_EN

•

The pattern verification is now in progress.

•

PRBSA_PASS contains a real time output that when low indicates the input PRBS pattern on RXAP/N

contains error.

•

PRBSB_PASS contains a real time output that when low indicates the input PRBS pattern on RXBP/N

contains error.

•

The following steps can be performed if the number of errors needs to be monitored:

–

Read 14.15:0 ERROR_COUNTER[15:0] and discard the value.

–

Read 14.15:0 ERROR_COUNTER[15:0], and verify 16’h0000 is read to confirm error free

operation. (as many times as desired during the duration of the test period)

4.19.2.2 27-1 / 223-1 / 231-1 PRBS Pin Based Testing

•

Note: PRBS TX does not support eighth rate mode.

•

Device Pin Setting(s):

–

Ensure PRBS_EN primary input pin is high.

–

PRBS Selection

•

PRBS 231-1 will be selected by default.

•

Reset Device:

–

Issue a hard or soft reset (RESET_N asserted –or- Write 1 to 0.15 GLOBAL_RESET)

•

Select SERDES Reference Clock Input:

–

If REFCLK_0_P/N used - Ensure REFCLK_A_SEL (or REFCLK_B_SEL if channel B is used)

primary input pin is low

–

If REFCLK_1_P/N used - Ensure REFCLK_A_SEL (or REFCLK_B_SEL if channel B is used)

primary input pin is high

•

Ensure a legal reference clock operation frequency is selected based on Appendix B (Continuous Rate

Device Configuration), and provision CHANNEL_CONTROL_1 register accordingly. (Note: Eighth

Rate TX Is Not Supported).

•

Serial Configuration

–

Configure the following bits per the desired application:

•

1.9:8 (LOOP_BANDWIDTH[1:0])

•

2.12:8 (TWPOST1[4:0])

•

2.7:4 (TWPRE[3:0])

•

2.3:0 (SWING[3:0])

•

8.14:12 (EQPRE[2:0])

•

8.11:10 (CDRTHR[1:0]) = 2’b01

•

8.9:8 (CDRFMULT[1:0]) = 2’b00

•

1.3:0 PLL_MULT[3:0]

•

1.7:6 RATE_TX[1:0]

•

1.5:4 RATE_RX[1:0]

•

Check SERDES PLL Status for Locked State

–

Poll 5.0 PLL_LOCK (per channel) until it is asserted (high).

•

Toggle ENRX

–

Write 1’b0 to 20.2 (ENRX)

–

Write 1’b1 to 20.2 (ENRX)

•

Select Test Pattern if either 27-1 or 223-1 PRBS Pattern is desired. Skip this step if 231-1 PRBS

Pattern is desired.

ELECTRICAL SPECIFICATIONS

Submit Documentation Feedback

Product Folder Link(s): TLK6002

TLK6002 датащи(PDF) 84 Page - Texas Instruments

TLK6002 датащи(HTML) 84 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

датащи скачать

ссылки URL