TLK6002 datasheet(55/96 Pages) TI

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TLK6002

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SLLSE34 – MAY 2010

Table 3-16. ARS_CONTROL_2

Address: 0x0B

Default: 0x7FFF

BIT(s)

NAME

DESCRIPTION

ACCESS

11.15:14

ARS_REF_FREQ[1:0]

Input reference clock frequency selection in ARS mode.

00 = If input reference clock frequency is 122.88 MHz.

01 = If input reference clock frequency is 153.60 MHz. (Default 2’b01)

10 = Reserved

11 = If input reference clock frequency is 307.20 MHz.

11.13:6

ARS_SBR_ENABLE[7:0]

Control to enable rate determination through ARS for each of the 8 supported bit

rates. ARS_SBR_ENABLE[7] for the highest serial bit rate and

ARS_SBR_ENABLE[0] for the lowest serial bit rate. Refer Table 2-6 for supported

serial bit rates.

11.5

RESERVED

For TI use only.

11.4:0

ARS_INTERVAL[20:16]

5 MSB’s of 21 bit wide counter defined in terms of number of REFCLK cycles to

determine amount of time that ARS state machine needs to stay in a particular

setting to achieve rate determination.

Wait time is calculated as ARS_INTERVAL[20:0] × 1024 REFCLK periods.

If ARS state machine does not achieve rate determination within the wait time

specified by this counter, ARS state machine will move into next lower serial rate

setting to achieve rate determination.

Table 3-17. ARS_CONTROL_3

Address: 0x0C

Default: 0xFFFF

BIT(s)

NAME

DESCRIPTION

ACCESS

12.15:0

ARS_INTERVAL[15:0]

16 LSB’s of 21 bit wide counter defined in terms of number of REFCLK cycles to

determine amount of time that ARS state machine needs to stay in a particular

setting to achieve rate determination.

Wait time is calculated as ARS_INTERVAL[20:0] × 1024 REFCLK periods.

If ARS state machine does not achieve rate determination within the wait time

specified by this counter, ARS state machine will move into next lowest serial rate

setting to achieve rate determination.

Table 3-18. ARS_CONTROL_4

Address: 0x0D

Default: 0x3000

BIT(s)

NAME

DESCRIPTION

ACCESS

13.15

RESERVED

For TI use only.

13.14

RESERVED

For TI use only.

13.13

RESERVED

For TI use only.

13.12

RESERVED

For TI use only.

13.11:0

RESERVED

For TI use only.

Table 3-19. ERROR_COUNTER

Address: 0x0E

Default: 0xFFFD

BIT(s)

NAME

DESCRIPTION

ACCESS

14.15:0

ERROR_COUNTER[15:0]

In functional mode if 8b/10b decoder is enabled, this counter reflects number of

COR

invalid code words (includes disparity errors) received by decoder.

In test pattern verification mode (7.12 = 1’b1), this counter reflects error count for the

test pattern selected through 7.10:8

When PRBS_EN pin is set, this counter reflects error count for selected PRBS

pattern. Counter value cleared to 16’h0000 when read.

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