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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC312XDP512F0MPVR датащи(PDF) 996 Page - Freescale Semiconductor, Inc |
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SC312XDP512F0MPVR датащи(HTML) 996 Page - Freescale Semiconductor, Inc |
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996 / 1348 page  Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 998 Freescale Semiconductor 24.0.5.9 ECLK Control Register (ECLKCTL) Read: Anytime. Write: Anytime. The ECLKCTL register is used to control the availability of the free-running clocks and the free-running clock divider. 76543210 R NECLK NCLKX2 0000 EDIV1 EDIV0 W Reset1 1. Reset values in emulation modes are identical to those of the target mode. Mode Dependent 1000000 Mode SS 01000000 Special Single-Chip ES 11000000 Emulation Single-Chip ST 01000000 Special Test EX 01000000 Emulation Expanded NS 11000000 Normal Single-Chip NX 01000000 Normal Expanded = Unimplemented or Reserved Figure 24-11. ECLK Control Register (ECLKCTL) Table 24-12. ECLKCTL Field Descriptions Field Description 7 NECLK No ECLK — This bit controls the availability of a free-running clock on the ECLK pin. Clock output is always active in emulation modes and if enabled in all other operating modes. 0 ECLK enabled 1 ECLK disabled 6 NCLKX2 No ECLKX2 — This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the internal bus clock. Clock output is always active in emulation modes and if enabled in all other operating modes. 0 ECLKX2 is enabled 1 ECLKX2 is disabled 1–0 EDIV[1:0] Free-Running ECLK Divider — These bits determine the rate of the free-running clock on the ECLK pin. The usage of the bits is shown in Table 24-13. Divider is always disabled in emulation modes and active as programmed in all other operating modes. |
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