SC312XDP512F0MPVR datasheet(95/1348 Pages) FREESCALE

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Chapter 2 Clocks and Reset Generator (S12CRGV6)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

WRTMASK

Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits

while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of

WCOP and CR[2:0].

0 Write of WCOP and CR[2:0] has an effect with this write of COPCTL

1 Write of WCOP and CR[2:0] has no effect with this write of COPCTL. (Does not count for “write once”.)

2–0

CR[1:0]

COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see Table 2-10). The COP

time-out period is OSCCLK period divided by CR[2:0] value. Writing a nonzero value to CR[2:0] enables the

COP counter and starts the time-out period. A COP counter time-out causes a system reset. This can be

avoided by periodically (before time-out) reinitializing the COP counter via the ARMCOP register.

While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at

highest time-out period (

2 24 cycles) in normal COP mode (Window COP mode disabled):

1) COP is enabled (CR[2:0] is not 000)

2) BDM mode active

3) RSBCK = 0

4) Operation in emulation or special modes

Table 2-10. COP Watchdog Rates1

1 OSCCLK cycles are referenced from the previous COP time-out reset

(writing 0x_55/0x_AA to the ARMCOP register)

CR2

CR1

CR0

OSCCLK

Cycles to Time-out

COP disabled

001

214

010

216

011

218

100

220

101

222

110

223

111

224

Table 2-9. COPCTL Field Descriptions (continued)

Field

Description

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