SC312XDP512F0MPVR datasheet(87/1348 Pages) FREESCALE

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Chapter 2 Clocks and Reset Generator (S12CRGV6)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

LVRF

Low Voltage Reset Flag — If low voltage reset feature is not available (see device speciﬁcation) LVRF always

reads 0. LVRF is set to 1 when a low voltage reset occurs. This ﬂag can only be cleared by writing a 1. Writing

a 0 has no effect.

0 Low voltage reset has not occurred.

1 Low voltage reset has occurred.

LOCKIF

PLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This ﬂag can only be cleared

by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE = 1), LOCKIF causes an interrupt request.

0 No change in LOCK bit.

1 LOCK bit has changed.

LOCK

Lock Status Bit — LOCK reﬂects the current state of PLL lock condition. This bit is cleared in self clock mode.

Writes have no effect.

0 PLL VCO is not within the desired tolerance of the target frequency.

1 PLL VCO is within the desired tolerance of the target frequency.

TRACK

Track Status Bit — TRACK reﬂects the current state of PLL track condition. This bit is cleared in self clock mode.

Writes have no effect.

0 Acquisition mode status.

1Tracking mode status.

SCMIF

Self Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This ﬂag can only be

cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE = 1), SCMIF causes an interrupt request.

0 No change in SCM bit.

1 SCM bit has changed.

SCM

Self Clock Mode Status Bit — SCM reﬂects the current clocking mode. Writes have no effect.

0 MCU is operating normally with OSCCLK available.

1 MCU is operating in self clock mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK

running at its minimum frequency fSCM.

Table 2-2. CRGFLG Field Descriptions (continued)

Field

Description

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