68HC705SP7 datasheet(167/230 Pages) FREESCALE

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Programmable Timer

Timer Control Register (TCR)

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Programmable Timer

ICIE — Input Capture Interrupt Enable

This read/write bit enables interrupts caused by an active signal on

the TCAP pin or from CPF2 flag bit of the analog subsystem voltage

comparator 2. Reset clears the ICIE bit.

1 = Input capture interrupts enabled

0 = Input capture interrupts disabled

OCIE — Output Compare Interrupt Enable

This read/write bit enables interrupts caused by an active match of the

output compare function. Reset clears the OCIE bit.

1 = Output compare interrupts enabled

0 = Output compare interrupts disabled

TOIE — Timer Overflow Interrupt Enable

This read/write bit enables interrupts caused by a timer overflow.

Reset clears the TOIE bit.

1 = Timer overflow interrupts enabled

0 = Timer overflow interrupts disabled

IEDG — Input Capture Edge Select

The state of this read/write bit determines whether a positive or

negative transition triggers a transfer of the contents of the timer

transitions on the TCAP pin or the CPF2 flag bit of voltage comparator

2. Resets have no effect on the IEDG bit.

1 = Positive edge (low-to-high transition) triggers input capture

0 = Negative edge (high-to-low transition) triggers input capture

NOTE:

The IEDG bit must be set when either Mode 2 or 3 of the analog

subsystem is being used for A/D conversions. Otherwise the input

capture will not occur on the rising edge of the comparator 2 flag.

OLVL — Output Compare Output Level Select

The state of this read/write bit determines whether a logic one or a

logic zero is transferred to the TCMP pin when a successful output

compare occurs. Resets clear the OLVL bit.

1 = Signal to TCMP pin goes high on output compare

0 = Signal to TCMP pin goes low on output compare

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