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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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68HC705SP7 датащи(PDF) 93 Page - Freescale Semiconductor, Inc |
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68HC705SP7 датащи(HTML) 93 Page - Freescale Semiconductor, Inc |
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93 / 230 page  Parallel Input/Output Port B MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 General Release Specification Parallel Input/Output When using the PB5/SDO pin, the following interactions must be noted: 1. If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB5/SDO pin buffer to be enabled and to be driven by the serial data output (SDO) from the SIOP. The pulldown device will be disabled in this case. 2. If the SIOP function is in control of the PB5/SDO pin, the DDRB5 and PB5 data register bits are still accessible to the CPU and can be altered or read without affecting the SIOP functionality. However, if the DDRB5 bit is cleared, reading the PB5 data register will return the current state of the PB5/SDO pin. 3. If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored in the DDRB5, PDIB5, and PB5 register bits will then control the PB5/SDO pin. 4. If the PB5/SDO pin is to be a digital input, then both the SPE bit in the SCR and the DDRB5 bit must be cleared. Depending on the external application, the pulldown device may also be disabled by setting the PDIB5 pulldown inhibit bit. 5. If the PB5/SDO pin is to be a digital output, then the SPE bit in the SCR must be cleared and the PDIB5 bit must be set. The pulldown device will be disabled in this case. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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