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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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68HC705SP7 датащи(PDF) 65 Page - Freescale Semiconductor, Inc |
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68HC705SP7 датащи(HTML) 65 Page - Freescale Semiconductor, Inc |
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65 / 230 page  Resets Reset States MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 General Release Specification Resets 5.6.2 I/O Registers A reset has the following effects on I/O registers: • Clears bits in data direction registers configuring pins as inputs: – DDRA5–DDRA0 in DDRA for port A – DDRB7–DDRB0 in DDRA for port B – DDRC7–DDRC0 in DDRC for port C * • Clears bits in pulldown inhibit registers to enable pulldown devices: – PDIA5–PDIA0 in PDRA for port A – PDIB7–PDIB0 in PDRB for port B – PDICH and PDICL in PDRA for port C * • Has no effect on port A, B, or C * data registers • Sets the IRQE bit in the interrupt status and control register (ISCR) 5.6.3 Core Timer A reset has the following effects on the core timer: • Clears the core timer counter register (CTCR) • Clears the core timer interrupt flag and enable bits in the core timer status and control register (CTSCR) • Sets the real-time interrupt rate selection bits (RT0 and RT1) such that the device will start with the longest real-time interrupt and longest COP timeout delays 5.6.4 COP Watchdog A reset clears the COP watchdog timeout counter. *Features related to Port C are only available on the 28-pin MC68HC705JP7 devices Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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