68HC705SP7 datasheet(163/230 Pages) FREESCALE

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Programmable Timer

Input Capture Registers (ICRH and ICRL)

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Programmable Timer

The input capture registers are made up of two 8-bit read-only registers

(ICRH and ICRL) as shown in Figure 11-7. The input capture edge

detector contains a Schmitt trigger to improve noise immunity. The edge

that triggers the counter transfer is defined by the input edge bit (IEDG)

in the TCR. Reset does not affect the contents of the input capture

registers.

The result obtained by an input capture will be one count higher than the

value of the free-running timer counter preceding the external transition.

This delay is required for internal synchronization. Resolution is affected

by the prescaler, allowing the free-running timer counter to increment

once every four internal clock cycles (eight oscillator clock cycles).

Reading the ICRH inhibits future captures until the ICRL is also read.

Reading the ICRL after reading the timer status register (TSR) clears the

ICF flag bit. There is no conflict between reading the ICRL and transfers

from the free-running timer counters. The input capture registers always

contain the free-running timer counter value which corresponds to the

most recent input capture.

NOTE:

To prevent interrupts from occurring between readings of the ICRH and

ICRL, set the I bit in the condition code register (CCR) before reading

ICRH and clear the I bit after reading ICRL.

$0014

Bit 7

654321

Bit 0

Read:

Bit 15

Bit 8

Write:

Reset:

Unaffected by Reset

$0015

Bit 7

654321

Bit 0

Read:

Bit 7

654321

Bit 0

Write:

Reset:

Unaffected by Reset

= Unimplemented

Figure 11-7. Input Capture Registers (ICRH and ICRL)

Freescale Semiconductor, Inc.

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