68HC705SP7 datasheet(168/230 Pages) FREESCALE

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Programmable Timer

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Programmable Timer

11.8 Timer Status Register (TSR)

The timer status register (TSR) shown in Figure 11-11 contains flags for

the following events:

•

An active signal on the TCAP pin or the CPF2 flag bit of voltage

comparator 2 in the analog subsystem, transferring the contents

of the timer registers to the input capture registers

•

A match between the 16-bit counter and the output compare

registers, transferring the OLVL bit to the PB4/AN4/TCMP pin if

that pin is set as an output

•

An overflow of the timer registers from $FFFF to $0000

Writing to any of the bits in the TSR has no effect. Reset does not

change the state of any of the flag bits in the TSR.

ICF — Input Capture Flag

The ICF bit is automatically set when an edge of the selected polarity

occurs on the TCAP pin. Clear the ICF bit by reading the timer status

of the input capture registers. Resets have no effect on ICF.

OCF — Output Compare Flag

The OCF bit is automatically set when the value of the timer registers

matches the contents of the output compare registers. Clear the OCF

bit by reading the timer status register with the OCF set and then

accessing the low byte (OCRL, $0017) of the output compare

registers. Resets have no effect on OCF.

$0013

Bit 7

654321

Bit 0

Read:

ICF

OCF

TOF

00000

Write:

Reset:

00000

= Unimplemented

U = Unaffected

Figure 11-11. Timer Status Register (TSR)

Freescale Semiconductor, Inc.

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