68HC705SP7 datasheet(165/230 Pages) FREESCALE

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Programmable Timer

Output Compare Registers (OCRH and OCRL)

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Programmable Timer

The planned action on the PB4/AN4/TCMP pin depends on the value

stored in the OLVL bit in the TCR, and it occurs when the value of the

16-bit free-running timer counter matches the value in the output

compare registers shown in Figure 11-9. These registers are read/write

bits and are unaffected by reset.

Writing to the OCRH before writing to the OCRL inhibits timer compares

until the OCRL is written. Reading or writing to the OCRL after reading

the TCR will clear the output compare flag bit (OCF). The output

compare OLVL state will be clocked to its output latch regardless of the

state of the OCF.

To prevent OCF from being set between the time it is read and the time

the output compare registers are updated, use the following procedure:

1. Disable interrupts by setting the I bit in the condition code register.

2. Write to the OCRH. Compares are now inhibited until OCRL is

written.

3. Read the TSR to arm the OCF for clearing.

4. Enable the output compare registers by writing to the OCRL. This

also clears the OCF flag bit in the TSR.

5. Enable interrupts by clearing the I bit in the condition code

$0016

Bit 7

654321

Bit 0

Read:

Bit 15

Bit 8

Write:

Reset:

Unaffected by Reset

$0017

Bit 7

654321

Bit 0

Read:

Bit 7

654321

Bit 0

Write:

Reset:

Unaffected by Reset

Figure 11-9. Output Compare Registers (OCRH and OCRL)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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