ADT7463ARQZ-R7 datasheet(37/52 Pages) ONSEMI

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REV. C

ADT7463

–37–

Table XI. Register 0x37 – Dynamic TMIN Control Register 2 (Power-On Default = 0x00)

Bit

Name

R/W*

Description

<2:0>

CYR1

Read/Write

3-Bit Remote 1 Cycle Value. These three bits define the delay time between making

subsequent TMIN adjustments in the control loop for the Remote 1 channel, in terms of

number of monitoring cycles. The system has associated thermal time constants that

need to be found to optimize the response of fans and the control loop.

Bits

Decrease Cycle

Increase Cycle

000

4 cycles (0.5 s)

8 cycles (1 s)

001

8 cycles (1 s)

16 cycles (2 s)

010

16 cycles (2 s)

32 cycles (4 s)

011

32 cycles (4 s)

64 cycles (8 s)

100

64 cycles (8 s)

128 cycles (16 s)

101

128 cycles (16 s)

256 cycles (32 s)

110

256 cycles (32 s)

512 cycles (64 s)

111

512 cycles (64 s)

1024 cycles (128 s)

<5:3>

CYL

Read/Write

3-Bit Local Temp Cycle Value. These three bits define the delay time between making

subsequent TMIN adjustments in the control loop for the local temperature channel, in

terms of number of monitoring cycles. The system has associated thermal time con-

stants that need to be found to optimize the response of fans and the control loop.

Bits

Decrease Cycle

Increase Cycle

000

4 cycles (0.5 s)

8 cycles (1 s)

001

8 cycles (1 s)

16 cycles (2 s)

010

16 cycles (2 s)

32 cycles (4 s)

011

32 cycles (4 s)

64 cycles (8 s)

100

64 cycles (8 s)

128 cycles (16 s)

101

128 cycles (16 s)

256 cycles (32 s)

110

256 cycles (32 s)

512 cycles (64 s)

111

512 cycles (64 s)

1024 cycles (128 s)

<7:6>

CYR2

Read/Write

2 LSBs of 3-Bit Remote 2 Cycle Value. The MSB of the 3-bit code resides in Dynamic

TMIN Control Register 1 (Reg. 0x36). These three bits define the delay time between

making subsequent TMIN adjustments in the control loop for the Remote 2 channel, in

terms of number of monitoring cycles. The system has associated thermal time con-

stants that need to be found to optimize the response of fans and the control loop.

Bits

Decrease Cycle

Increase Cycle

000

4 cycles (0.5 s)

8 cycles (1 s)

001

8 cycles (1 s)

16 cycles (2 s)

010

16 cycles (2 s)

32 cycles (4 s)

011

32 cycles (4 s)

64 cycles (8 s)

100

64 cycles (8 s)

128 cycles (16 s)

101

128 cycles (16 s)

256 cycles (32 s)

110

256 cycles (32 s)

512 cycles (64 s)

111

512 cycles (64 s)

1024 cycles (128 s)

*This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to this register fail.

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