ADT7463ARQZ-R7 datasheet(31/52 Pages) ONSEMI

31 / 52 page

REV. C

ADT7463

–31–

By reading the PWMx current duty cycle registers, users can

keep track of the current duty cycle on each PWM output, even

when the fans are running in automatic fan speed control mode

or acoustic enhancement mode.

VARY PWM DUTY

CYCLE WITH 8-BIT

RESOLUTION

Figure 38. Control PWM Duty Cycle Manually with

a Resolution of 0.39%

OPERATING FROM 3.3 V STANDBY

The ADT7463 has been specifically designed to operate from a

3.3 V STBY supply. In computers that support S3 and S5

states, the core voltage of the processor is lowered in these states.

If using the dynamic TMIN mode, lowering the core voltage of

the processor would change the CPU temperature and change

the dynamics of the system under dynamic TMIN control. Like-

wise, when monitoring THERM, the THERM timer should

be disabled during these states.

DYNAMIC TMIN CONTROL REGISTER 1 (REG. 0x36)

<1> VCCPLO = 1

When the power is supplied from 3.3 V STBY and the VCCP

voltage drops below the VCCP low limit, the following occurs:

• Status Bit 1 (VCCP) in Status Register 1 gets set.

• SMBALERT gets generated if enabled.

• THERM monitoring is disabled. The THERM timer

should hold its value prior to the S3 or S5 state.

• Dynamic TMIN control is disabled. This prevents TMIN

from being adjusted due to an S3 or S5 state.

• The ADT7463 is prevented from entering the shutdown

state.

Once the core voltage, VCCP, goes above the VCCP low limit, every-

thing gets re-enabled and the system resumes normal operation.

Note that since other voltages can drop or be turned off during

a low power state, these voltage channels set status bits or

generate SMBALERTs. It is still necessary to mask out these

channels prior to entering a low power state using the interrupt

mask registers. When exiting the low power state, the mask bits

can be cleared. This prevents the device from generating

unwanted SMBALERTs during the low power state.

XOR TREE TEST MODE

The ADT7463 includes an XOR Tree Test Mode. This mode is

useful for in-circuit test equipment at board-level testing. By

applying stimulus to the pins included in the XOR Tree, it is

possible to detect opens or shorts on the system board. Figure 39

shows the signals that are exercised in the XOR Tree Test Mode.

PWM1/XTO

PWM3

PWM2

TACH4

TACH3

TACH2

TACH1

VID4

VID3

VID2

VID1

VID0

Figure 39. XOR Tree Test

The XOR Tree Test is invoked by setting Bit 0 (XEN) of the

XOR Tree Test Enable Register (Reg. 0x6F).

POWER-ON DEFAULT

The ADT7463 does not monitor temperature and fan speed by

default on power-up. Monitoring of temperature and fan speed

is enabled by setting the Start Bit in Configuration Register 1

(Bit 0, Address 0

×40) to 1. The fans run at full speed on power-

up. This is because the BHVR bits (Bits 7:5) in the PWMx

configuration registers are set to 100 (fans run full speed) by default.

Rev. 4 | Page 31 of 52 | www.onsemi.com

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