ADT7463ARQZ-R7 datasheet(23/52 Pages) ONSEMI

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REV. C

ADT7463

–23–

THERM TIMER

The ADT7463 has an internal timer to measure THERM asser-

tion time. For example, the THERM input may be connected

to the PROCHOT output of a Pentium 4 CPU and measure

system performance. The THERM input may also be connected

to the output of a trip point temperature sensor.

The timer is started on the assertion of the ADT7463’s

THERM input and stopped on the negation of the pin. The

timer counts THERM times cumulatively, i.e., the timer

resumes counting on the next THERM assertion. The THERM

timer continues to accumulate THERM assertion times until

the timer is read (it is cleared on read) or until it reaches full

scale. If the counter reaches full scale, it stops at that reading

until cleared.

The 8-bit THERM timer register (Reg. 0x79) is designed such

that Bit 0 gets set to 1 on the first THERM assertion. Once the

cumulative THERM assertion time has exceeded 45.52 ms, Bit

1 of the THERM timer gets set and Bit 0 now becomes the LSB

of the timer with a resolution of 22.76 ms.

THERM

TIMER

(REG. 0x79)

THERM

0 0 0 0001 0

7 6 54 3 21 0

THERM ASSERTED

22.76ms

THERM

ACCUMULATE THERM LOW

ASSERTION TIMES

THERM ASSERTED

45.52ms

0 0 00010 1

7 6 54 3 21 0 THERM ASSERTED 113.8ms

(91.04ms + 22.76ms)

THERM

TIMER

(REG. 0x79)

THERM

ACCUMULATE THERM LOW

ASSERTION TIMES

0 0 0 0000 1

7 6 54 3 21 0

THERM

TIMER

(REG. 0x79)

Figure 26. Understanding the THERM Timer

Figure 26 illustrates how the THERM timer behaves as the

THERM input is asserted and negated. Bit 0 gets set on the first

THERM assertion detected. This bit remains set until such time

as the cumulative THERM assertions exceed 45.52 ms. At this

time, Bit 1 of the THERM timer gets set, and Bit 0 is cleared.

Bit 0 now reflects timer readings with a resolution of 22.76 ms.

When using the THERM timer, be aware of the following:

After a THERM timer read (Reg. 0x79):

a) The contents of the timer get cleared on read.

b) The F4P bit (Bit 5) of Status Register 2 needs to be cleared

(assuming the THERM limit has been exceeded).

If the THERM timer is read during a THERM assertion, then

the following will happen:

a) The contents of the timer are cleared.

b) Bit 0 of the THERM timer is set to 1 (since a THERM

assertion is occurring).

c) The THERM timer increments from zero.

d) If the THERM limit (Reg. 0x7A) = 0x00, then the F4P bit

gets set.

Generating SMBALERT Interrupts from THERM Events

The ADT7463 can generate SMBALERTs when a programmable

THERM limit has been exceeded. This allows the systems

designer to ignore brief, infrequent THERM assertions, while

capturing longer THERM events. Register 0x7A is the THERM

Limit Register. This 8-bit register allows a limit from 0 seconds

(first THERM assertion) to 5.825 seconds to be set before an

SMBALERT is generated. The THERM timer value is compared

with the contents of the THERM limit register. If the THERM

timer value exceeds the THERM limit value, then the F4P bit

(Bit 5) of Status Register 2 gets set, and an SMBALERT is

generated. Note that the F4P bit (Bit 5) of Mask Register 2

(Reg. 0x75) masks out SMBALERTs if this bit is set to 1, al-

though the F4P bit of Interrupt Status Register 2 still gets set if

the THERM limit is exceeded.

Figure 27 is a Functional Block Diagram of the THERM timer,

limit, and associated circuitry. Writing a value of 0x00 to the

THERM limit register (Reg. 0x7A) causes SMBALERT to

be generated on the first THERM assertion. A THERM limit

value of 0x01 generates an SMBALERT once cumulative THERM

assertions exceed 45.52 ms.

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