ADT7463ARQZ-R7 datasheet(20/52 Pages) ONSEMI

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REV. C

–20–

ADT7463

INT

LOW LIMIT

TEMP =

LOW LIMIT

Figure 18. Temperature = Low Limit: INT Occurs

NO INT

HIGH LIMIT

TEMP =

HIGH LIMIT

21.00C

Figure 19. Temperature = High Limit: No INT

HIGH LIMIT

INT

TEMP >

HIGH LIMIT

Figure 20. Temperature > High Limit: INT Occurs

Analog Monitoring Cycle Time

The analog monitoring cycle begins when a 1 is written to the

start bit (Bit 0) of Configuration Register 1 (Reg. 0x40). The ADC

measures each analog input in turn and as each measurement is

completed, the result is automatically stored in the appropriate

value register. This round-robin monitoring cycle continues

unless disabled by writing a 0 to Bit 0 of Configuration Register 1.

Because the ADC is normally left to free-run in this manner, the

time taken to monitor all the analog inputs is normally not of

interest, since the most recently measured value of any input

can be read out at any time.

For applications where the monitoring cycle time is important,

it is easily calculated.

The total number of channels measured is:

• Four dedicated supply voltage inputs

• 3.3 VSTBY or 5 V supply (VCC pin)

• Local temperature

• Two remote temperatures

As mentioned previously, the ADC performs round-robin

conversions and takes 11.38 ms for each voltage measurement,

12 ms for a local temperature reading, and 25.5 ms for each remote

temperature reading.

The total monitoring cycle time for averaged voltage and tempera-

ture monitoring is therefore nominally

5 11 38

2 25 5

120

() + +×

() =

Fan TACH measurements are made in parallel and are not

synchronized with the analog measurements in any way.

Status Registers

The results of limit comparisons are stored in Status Registers 1

and 2. The status register bit for each channel reflects the status

of the last measurement and limit comparison on that channel.

If a measurement is within limits, the corresponding status register

bit is cleared to 0. If the measurement is out-of-limits, the corre-

sponding status register bit is set to 1.

The state of the various measurement channels may be polled

by reading the status registers over the serial bus. In Bit 7 (OOL)

of Status Register 1 (Reg. 0x41), 1 means that an out-of-limit

event has been flagged in Status Register 2. This means that a

user need only read Status Register 2 when this bit is set. Alter-

natively, Pin 10 or Pin 22 can be configured as an SMBALERT

output. This automatically notifies the system supervisor of an

out-of-limit condition. Reading the status registers clears the

appropriate status bit as long as the error condition that caused

the interrupt has cleared. Status register bits are “sticky.” When-

ever a status bit gets set, indicating an out-of-limit condition,

it remains set even if the event that caused it has gone away

(until read). The only way to clear the status bit is to read the

status register after the event has gone away. Interrupt status

mask registers (Reg. 0x74, 0x75) allow individual interrupt

sources to be masked from causing an SMBALERT. However,

if one of these masked interrupt sources goes out-of-limit, its

associated status bit gets set in the interrupt status registers.

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