ADS1258IPHPREP datasheet(21/57 Pages) TI

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CLK

128(411b*DR ) 4.265625 ) TD)

2CHOP

CLK

128(411b*DR ) CHOP(4.265625 ) TD))

2CHOP

Analog

Modulator

sinc5

Filter

Programmable

Averager

Data Rate = f

CLK/128

Modulator Rate = f

CLK/2

Num_Ave

Data Rate(1) = f

CLK/(128 × Num_Ave)

NOTE: (1) Data rate for Fixed−Channel Mode, Chop = 0, Delay = 0.

ADS1258-EP

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SBAS445C – MARCH 2009 – REVISED DECEMBER 2009

ADC

rate—filter more for higher resolution, filter less for

higher data rate. The filter is comprised of two

The ADC block of the ADS1258 is composed of two

sections, a fixed filter followed by a programmable

blocks: a modulator and a digital filter.

filter. Figure 42 shows the block diagram of the filter.

Data is supplied to the filter from the analog

Modulator

modulator at a rate of fCLK/2. The fixed filter is a

fifth-order sinc filter with a decimation value of 64 that

The modulator converts the analog input voltage into

outputs data at a rate of fCLK/128. The second stage

a Pulse Code Modulated (PCM) data stream. When

of the filter is a programmable averager (first-order

the level of differential analog input (ADCINP –

sinc filter) with the number of averages set by the

ADCINN) is near the level of the reference voltage,

DRATE[1:0] bits.

the '1' density of the PCM data stream is at its

highest. When the level of the differential analog input

The data rate depends upon the system clock

is near zero, the PCM '0' and '1' densities are nearly

frequency (fCLK) and the converter configuration. The

equal.

The

fourth-order

modulator

shifts

the

data rate can be computed by Equation 2 or

quantization noise to a high frequency (out of the

Equation 3:

passband) where the digital filter can easily remove it.

Data Rate (Auto-Scan):

The modulator continuously chops the input, resulting

in excellent offset and offset drift performance. It is

important to note that offset or offset drift originating

(2)

from the external circuitry is not removed by the

Data Rate (Fixed-Channel Mode):

modulator chopping. These errors can be effectively

removed by using the external chopping feature of

the ADS1258 (see the External Chopping section).

(3)

Where:

Digital Filter

DR = DRATE[1:0] register bits (binary).

The programmable low-pass digital filter receives the

CHOP = Chop register bit.

modulator output and produces a high-resolution

TD = time delay value given in Table 5 from the

digital output. By adjusting the amount of filtering,

DLY[2:0] register bits (128/fCLK periods).

tradeoffs can be made between resolution and data

Figure 42. Block Diagram of Digital Filter

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