ADS1258IPHPREP datasheet(7/57 Pages) TI

7 / 57 page

SCLK

(1)

DIN

DOUT

SCLK

CSSC

SPW

DIST

DIHD

SPW

CSDO

Hi-Z

CSPW

DOPD

DOHD

NOTE:(1)

canbetiedlow.

DRDY

DOUT

DRDY

DDO

ADS1258-EP

www.ti.com

SBAS445C – MARCH 2009 – REVISED DECEMBER 2009

PARAMETER MEASUREMENT INFORMATION

Figure 1. Serial Interface Timing

SERIAL INTERFACE TIMING CHARACTERISTICS

At TA= –40°C to +105°C

(1) and DVDD = 2.7 V to 5.25 V, unless otherwise noted.

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

tSCLK

SCLK Period

τCLK

(2)

tSPW

SCLK High or Low Pulse Width (exceeding max resets SPI interface)

0.8

4096(3)

τCLK

tCSSC

CS Low to First SCLK: Setup Time(4)

2.5

τCLK

tDIST

Valid DIN to SCLK Rising Edge: Setup Time

tDIHD

Valid DIN to SCLK Rising Edge: Hold Time

tDOPD

SCLK Falling Edge to Valid New DOUT: Propagation Delay(5)

tDOHD

SCLK Falling Edge to Old DOUT Invalid: Hold Time

tCSDO

CS High to DOUT Invalid (tri-state)

τCLK

tCSPW

CS Pulse Width High

τCLK

(1)

Ensured by characterization only.

(2)

τCLK = master clock period = 1/fCLK.

(3)

Programmable to 256

τCLK.

(4)

CS can be tied low.

(5)

DOUT load = 20 pF || 100k

Ω to DGND.

Figure 2. DRDY Update Timing

DRDY UPDATE TIMING CHARACTERISTICS

SYMBOL

DESCRIPTION

TYP

UNITS

t DRDY

DRDY High Pulse Width Without Data Read

τCLK

tDDO

Valid DOUT to DRDY Falling Edge (CS = 0)

0.5

τCLK

Submit Documentation Feedback

Product Folder Link(s): ADS1258-EP

ADS1258IPHPREP датащи(PDF) 7 Page - Texas Instruments

ADS1258IPHPREP датащи(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

датащи скачать

ссылки URL