ADS1258IPHPREP datasheet(20/57 Pages) TI

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Ω

32.768kHz(1)

4.7pF

22nF

CLKSEL XTAL1

XTAL2

PLLCAP

AVSS

CLKIO

Clock Output

(15.729MHz)

0V to

−2.5V

NOTE: (1) Parallel resonant type, C

L = 12.5pF, ESR = 35kΩ (max).

Place the crystal and load capacitors as close as possible to the device pins.

Oscillator

andPLL

MUX

CLKENB

Bit

InternalMasterClock(f

)

CLK

CLKSEL

CLKIO

XTAL1

XTAL2

PLL

Ω

CLKSEL

XTAL1

XTAL2

PLLCAP

DVDD

CLKIO

Clock Input

(16MHz)

2.7V

to 5V

No Connection

ADS1258-EP

SBAS445C – MARCH 2009 – REVISED DECEMBER 2009

www.ti.com

MASTER CLOCK (fCLK)

The ADS1258 oversamples the analog input at a high

rate. This requires a high-frequency master clock to

be supplied to the converter. As shown in Figure 39,

the clock comes from either an internal oscillator (with

external crystal), or an external clock source.

Figure 40. Crystal Oscillator Connection

Table 1. System Clock Source

CLKSEL

CLKENB

CLOCK SOURCE

BIT

CLKIO FUNCTION

32.768 kHz

Disabled

Crystal Oscillator

(internally grounded)

Figure 39. Clock Generation Block Diagram

32.768 kHz

Output (15.729 MHz)

Crystal Oscillator

The CLKSEL pin determines the source of the

External Clock Input

Input (16 MHz)

system clock, as shown in Table 1. The CLKIO pin

functions as an input or as an output. When the

Table 2. Approved Crystal Vendors

CLKSEL pin is set to '1', CLKIO is configured as an

input to receive the master clock. When the CLKSEL

VENDOR

CRYSTAL PRODUCT

pin is set to '0', the crystal oscillator generates the

Epson

C-001R

clock. The CLKIO pin can then be configured to

output the master clock. When the clock output is not

External Clock Input

needed, it can be disabled to reduce device power

consumption.

When using an external clock to operate the device,

apply the master clock to the CLKIO pin. For this

Crystal Oscillator

mode, the CLKSEL pin is tied high. CLKIO then

becomes an input, as shown in Figure 41.

An on-chip oscillator and Phase-Locked Loop (PLL)

together with an external crystal can be used to

generate the system clock. For this mode, tie the

CLKSEL pin low. A 22nF PLL filter capacitor,

connected from the PLLCAP pin to the AVSS pin, is

required. The internal clock of the PLL can be output

to the CLKIO to drive other converters or controllers.

If not used, disable the clock output to reduce device

power consumption; see Table 1 for settings. The

clock output is enabled by a register bit setting

(default is ON). Figure 40 shows the oscillator

connections. Place these components as close to the

Figure 41. External Clock Connection

pins as possible to avoid interference and coupling.

Do not connect XTAL1 or XTAL2 to any other logic.

The oscillator start-up time may vary, depending on

Make sure to use a clock source clean from jitter or

the crystal and ambient temperature. The user should

interference. Ringing or under/overshoot should be

verify the oscillator start-up time.

avoided. A 50

Ω resistor in series with the CLKIO pin

(placed close to the source) can often help.

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