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SERIAL INTERFACE

Register Initialization

D15 D14 D13 D12 D11 D10 D9

D8 D7 D6 D5 D4 D3 D2 D1 D0

A7 A6 A5 A4 A3 A2 A1 A0

CS

SCLK

SDATA

DatalatchedonrisingedgeofSCLK

StartSequence

EndSequence

t

6

t

4

t

2

t

7

t

3

t

5

t

1

ADS5281

ADS5282

SBAS397H – DECEMBER 2006 – REVISED MARCH 2008

The ADS528x has a set of internal registers that can be accessed through the serial interface formed by pins CS

(chip select, active low), SCLK (serial interface clock), and SDATA (serial interface data). When CS is low, the

following actions occur:

• Serial shift of bits into the device is enabled

• SDATA (serial data) is latched at every rising edge of SCLK

• SDATA is loaded into the register at every 24th SCLK rising edge

If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of

24-bit words within a single active CS pulse. The first eight bits form the register address and the remaining 16

bits form the register data. The interface can work with SCLK frequencies from 20MHz down to very low speeds

(a few hertz) and also with a non-50% SCLK duty cycle.

After power-up, the internal registers must be initialized to the respective default values. Initialization can be

done in one of two ways:

1. Through a hardware reset, by applying a low-going pulse on the RESET pin; or

2. Through a software reset; using the serial interface, set the RST bit high. Setting this bit initializes the

internal registers to the respective default values and then self-resets the RST bit low. In this case, the

RESET pin stays high (inactive).

After all registers have been initialized to their default values through a RESET operation, the registers detailed

in the Initialization Registers table must be written into. This process must be done after every hardware or

software RESET operation in order to reconfigure the device for the best mode of operation.

SERIAL INTERFACE TIMING

ADS528x

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

SCLK period

50

ns

SCLK high time

20

ns

SCLK low time

20

ns

Data setup time

5

ns

Data hold time

5

ns

CS fall to SCLK rise

8

ns

Time between last SCLK rising edge to CS rising edge

8

ns

Copyright © 2006–2008, Texas Instruments Incorporated

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Product Folder Link(s): ADS5281 ADS5282