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0.75

0.55

0.35

0.15

-

0.05

-

0.25

-

0.65

Code(LSB)

0

4096

3072

2048

2560

1536

3584

1024

512

-

0.45

f =65MSPS

f

=5MHz

S

IN

0.35

0.25

0.15

0.05

-

0.05

-

0.15

-

0.35

Code(LSB)

0

4096

3072

2048

2560

1536

3584

1024

512

-

0.25

f =65MSPS,f

=5MHz

S

IN

170

130

110

90

70

30

ClockFrequency(MSPS)

5

75

35

25

15

45

I

LVDD

I

AVDD

ZeroInputonAllChannels

InternalReferenceMode

150

55

50

65

0.70

0.68

0.66

0.64

0.62

0.60

0.58

0.56

0.54

0.52

0.50

0

1

2

3

4

5

6

OverloadSignalAmplitude(dBFS)

f =50MSPS

f

=5MHz

S

IN

StandardDeviationof

2ndPointAfterOverload

StandardDeviationof

1stPointAfterOverload

t

S

16384t (Group1)

S

Set1,Point1(of16)

Set1,Point2(of16)

Firstpointafteroverload(Set1)

Firstpointafteroverload(Set2)

Secondpointafteroverload(Set2)

Secondpointafteroverload(Set1)

Overload

Amplitude

NOTES:

Inputsinewavephaseisrepetitiveover16384clockcycles.

16suchrepetitivegroups(of16384clockcycles)arecaptured–atotalof262,144points.

Standarddeviationofeverysetof

areanalyzedoverthe16groups.

Worstcaseofallsuchstandarddeviationsareplottedinthegraphs.

firstandsecondpointsafteroverload

+FS

-

FS

0.64

0.62

0.60

0.58

0.56

0.54

0.52

0

1

2

3

4

5

6

OverloadSignalAmplitude(dBFS)

f =65MSPS

f

=5MHz

S

IN

StandardDeviationof

2ndPointAfterOverload

StandardDeviationof

1stPointAfterOverload

ADS5281

ADS5282

SBAS397H – DECEMBER 2006 – REVISED MARCH 2008

TYPICAL CHARACTERISTICS (continued)

clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input

current setting = 3.5mA, unless otherwise noted.

INTEGRAL NONLINEARITY

DIFFERENTIAL NONLINEARITY

Figure 28.

Figure 29.

AVDD AND LVDD POWER-SUPPLY CURRENTS

vs CLOCK FREQUENCY

OVERLOAD RECOVERY AT 50MSPS

Figure 30.

Figure 31.

OVERLOAD RECOVERY AT 65MSPS

Figure 32.

Figure 33. Overload Recovery

Copyright © 2006–2008, Texas Instruments Incorporated

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