ADS5281IPFPR datasheet(34/44 Pages) TI

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INPUT OVER-VOLTAGE RECOVERY

REF

SET

0.1 F

2.2 F

56.2k

2.2 F

0.1 F

ADS528x

REFERENCE CIRCUIT

VREF =1.5V+

1.5V

(4)

VREF =1.5V

1.5V

(5)

ADS5281

ADS5282

SBAS397H – DECEMBER 2006 – REVISED MARCH 2008

The

differential

peak-to-peak

full-scale

range

supported by the ADS528x is nominally 2.0V. The

ADS528x

specially

designed

handle

over-voltage

condition

where

the

differential

peak-to-peak voltage can be up to twice the ADC

full-scale range. If the input common-mode is not

considerably off from VCM during overload (less than

300mV around the nominal value of 1.5V), recovery

from an over-voltage pulse input of twice the

amplitude of a full-scale pulse is expected to be

within one clock cycle when the input switches from

overload to zero signal.

Figure 42. Suggested Decoupling on the

Reference Pins

The digital beam-forming algorithm in an ultrasound

system relies on gain matching across all receiver

The device also supports the use of external

channels. A typical system would have about 12 octal

reference voltages. There are two methods to force

ADCs on the board. In such a case, it is critical to

the references externally. The first method involves

ensure that the gain is matched, essentially requiring

pulling INT/EXT low and forcing externally REFT and

the reference voltages seen by all the ADCs to be the

REFB to 2.5V and 0.5V nominally, respectively. In this

same. Matching references within the eight channels

mode, the internal reference buffer goes to a 3-state

of a chip is done by using a single internal reference

output. The external reference driving circuit should

voltage buffer. Trimming the reference voltages on

be designed to provide the required switching current

each

chip

during

production

ensures

that

the

for the eight ADCs inside the chip. It should be noted

reference voltages are well-matched across different

that in this mode, VCM and ISET continue to be

chips.

generated from the internal bandgap voltage, as in

the internal reference mode. It is therefore important

All bias currents required for the internal operation of

to ensure that the common-mode voltage of the

the device are set using an external resistor to

externally-forced

reference

voltages

matches

ground at the ISET pin. Using a 56.2kΩ resistor on ISET

within 50mV of VCM.

generates an internal reference current of 20

µA. This

current is mirrored internally to generate the bias

The second method of forcing the reference voltages

current for the internal blocks. Using a larger external

externally can be accessed by pulling INT/EXT low,

resistor at ISET reduces the reference bias current and

and programming the serial interface to drive the

thereby scales down the device operating power.

external reference mode through the VCM pin (register

However, it is recommended that the external resistor

bit called EXT_REF_VCM). In this mode, VCM

be within 10% of the specified value of 56.2k

Ω so

becomes configured as an input pin that can be

that the internal bias margins for the various blocks

driven from external circuitry. The internal reference

are proper.

buffers driving REFT and REFB are active in this

mode. Forcing 1.5V on the VCM pin in the mode

Buffering the internal bandgap voltage also generates

results in REFT and REFB coming to 2.5V and 0.5V,

the common-mode voltage VCM, which is set to the

respectively. In general, the voltages on REFT and

midlevel of REFT and REFB, and is accessible on a

REFB in this mode are given by Equation 4 and

pin (pin 65 in TQFP-80 package, pin 53 in QFN-64

Equation 5, respectively:

package). It is meant as a reference voltage to derive

the input common-mode if the input is directly

coupled. It can also be used to derive the reference

common-mode voltage in the external reference

mode. The suggested decoupling for the reference

pins is shown in Figure 42.

The state of the reference voltage internal buffers

during various combinations of the PD, INT/EXT, and

EXT_REF_VCM register bits is described in Table 7.

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