PIC18F23K20-ESLASHML datasheet(114/456 Pages) MICROCHIP

114 / 456 page

PIC18F2XK20/4XK20

DS41303G-page 114

 2010 Microchip Technology Inc.

9.6

PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of periph-

eral interrupt sources, there are two Peripheral Interrupt

Enable registers (PIE1 and PIE2). When IPEN = 0, the

PEIE bit must be set to enable any of these peripheral

interrupts.

PIE1: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 1

R/W-0

PSPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)

= Enables the PSP read/write interrupt

= Disables the PSP read/write interrupt

bit 6

ADIE: A/D Converter Interrupt Enable bit

= Enables the A/D interrupt

= Disables the A/D interrupt

bit 5

RCIE: EUSART Receive Interrupt Enable bit

= Enables the EUSART receive interrupt

= Disables the EUSART receive interrupt

bit 4

TXIE: EUSART Transmit Interrupt Enable bit

= Enables the EUSART transmit interrupt

= Disables the EUSART transmit interrupt

bit 3

SSPIE: Master Synchronous Serial Port Interrupt Enable bit

= Enables the MSSP interrupt

= Disables the MSSP interrupt

bit 2

CCP1IE: CCP1 Interrupt Enable bit

= Enables the CCP1 interrupt

= Disables the CCP1 interrupt

bit 1

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

= Enables the TMR2 to PR2 match interrupt

= Disables the TMR2 to PR2 match interrupt

bit 0

TMR1IE: TMR1 Overflow Interrupt Enable bit

= Enables the TMR1 overflow interrupt

= Disables the TMR1 overflow interrupt

Note 1:

The PSPIE bit is unimplemented on 28-pin devices and will read as ‘0’.

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