PIC18F23K20-ESLASHML datasheet(112/456 Pages) MICROCHIP

112 / 456 page

PIC18F2XK20/4XK20

DS41303G-page 112

 2010 Microchip Technology Inc.

9.5

PIR Registers

The PIR registers contain the individual flag bits for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are two Peripheral Interrupt

Request Flag registers (PIR1 and PIR2).

Note 1: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE of the INTCON

2: User software should ensure the appropri-

ate interrupt flag bits are cleared prior to

enabling an interrupt and after servicing

that interrupt.

PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

R/W-0

R-0

R/W-0

PSPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)

= A read or a write operation has taken place (must be cleared by software)

= No read or write has occurred

bit 6

ADIF: A/D Converter Interrupt Flag bit

= An A/D conversion completed (must be cleared by software)

= The A/D conversion is not complete or has not been started

bit 5

RCIF: EUSART Receive Interrupt Flag bit

= The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)

= The EUSART receive buffer is empty

bit 4

TXIF: EUSART Transmit Interrupt Flag bit

= The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)

= The EUSART transmit buffer is full

bit 3

SSPIF: Master Synchronous Serial Port Interrupt Flag bit

= The transmission/reception is complete (must be cleared by software)

= Waiting to transmit/receive

bit 2

CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

= A TMR1 register capture occurred (must be cleared by software)

= No TMR1 register capture occurred

Compare mode:

= A TMR1 register compare match occurred (must be cleared by software)

= No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 1

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

= TMR2 to PR2 match occurred (must be cleared by software)

= No TMR2 to PR2 match occurred

bit 0

TMR1IF: TMR1 Overflow Interrupt Flag bit

= TMR1 register overflowed (must be cleared by software)

= TMR1 register did not overflow

Note 1: The PSPIF bit is unimplemented on 28-pin devices and will read as ‘0’.

PIC18F23K20-E/ML датащи(PDF) 112 Page - Microchip Technology

PIC18F23K20-E/ML датащи(HTML) 112 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL