SC18IM700IPW datasheet(15/22 Pages) NXP

15 / 22 page

SC18IM700_2

Product data sheet

Rev. 02 — 10 August 2007

15 of 22

NXP Semiconductors

SC18IM700

Master I2C-bus controller with UART interface

11. Static characteristics

[1]

Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.

[2]

See Table 10 “Limiting values” for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition, VOL/VOH may

exceed the related speciﬁcation.

[3]

Pin capacitance is characterized but not tested.

[4]

Measured with GPIO in quasi-bidirectional mode.

[5]

Measured with GPIO in high-impedance mode.

[6]

GPIO in quasi-bidirectional mode with weak pull-up (applies to all GPIO pins with pull-ups). Does not apply to open-drain pins.

[7]

GPIO pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is

highest when VI is approximately 2 V.

Table 11.

Static characteristics

VDD = 2.4 V to 3.6 V; Tamb = −40 °Cto+85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ[1]

Max

Unit

IDD

supply current

VDD = 3.6 V

Operating mode; f = 7.3728 MHz

Idle mode; f = 7.3728 MHz

3.25

Power-down mode (sleep);

GPIO0 to GPIO7 as inputs;

inputs at VDD

-50

µA

VPOR

power-on reset voltage

0.2

Vth(HL)

negative-going threshold

voltage

except SCL, SDA

0.22VDD

0.4VDD

-V

VIL

LOW-level input voltage

SCL, SDA only

−0.5

0.3VDD

Vth(LH)

positive-going threshold

voltage

except SCL, SDA

0.6VDD

0.7VDD

VIH

HIGH-level input voltage SCL, SDA only

0.7VDD

5.5

VOL

LOW-level output

voltage

IOL =20mA

[2] -

0.6

1.0

IOL = 3.2 mA

[2] -

0.2

0.3

VOH

HIGH-level output

voltage

IOH = −20 mA; Push-pull mode;

GPIO3 to GPIO7

0.8VDD

IOH = −3.2 mA; Push-pull mode;

GPIO0 to GPIO2

VDD − 0.7 VDD − 0.4 -

IOH = −20 mA; quasi-bidirectional

mode; all GPIOs

VDD − 0.3 VDD − 0.2 -

Cio

input/output capacitance

[3] -

IIL

LOW-level input current

logic 0; all ports; VI = 0.4 V

[4] --

−80

µA

ILI

input leakage current

all ports; VI =VIL or VIH

[5] --

−10

µA

IT(HL)

negative-going transition

current

logic 1-to-0; all ports; VI = 2.0 V at

VDD = 3.6 V

[6][7]

−30

−450

µA

RRESET_N(int)

internal pull-up

resistance on pin

RESET

Ω

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