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SC18IM700IPW датащи(PDF) 8 Page - NXP Semiconductors

номер детали SC18IM700IPW
подробное описание детали  Master I2C-bus controller with UART interface
PDF  22 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

SC18IM700IPW датащи(HTML) 8 Page - NXP Semiconductors

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SC18IM700_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 10 August 2007
8 of 22
NXP Semiconductors
SC18IM700
Master I2C-bus controller with UART interface
8.
I2C-bus serial interface
The I2C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
• Bidirectional data transfer between masters and slaves
• Multi-master bus (no central master)
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
A typical I2C-bus configuration is shown in Figure 12. The SC18IM700 device provides a
byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.
Fig 12. I2C-bus configuration
RPU
002aab801
VDD
SC18IM700
I2C-BUS
DEVICE
I2C-BUS
DEVICE
I2C-bus
SDA
SCL
RPU



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